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1. 发明申请

US20120280356A1 UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE 审中-公开
标题翻译：在基板和结构结构中均匀分布的井和隔离区
公开(公告)号：US20120280356A1
公开(公告)日：2012-11-08
申请号：US13552695
申请日：2012-07-19
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
IPC分类号： H01L29/06
CPC分类号： H01L21/76232
摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
摘要翻译：本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。距离对于每个沟槽和每个相邻的隔离区域是成比例的。

2. 发明申请

US20120128033A1 THERMAL SENSOR FOR SEMICONDUCTOR CIRCUITS 失效
标题翻译：用于半导体电路的热传感器
公开(公告)号：US20120128033A1
公开(公告)日：2012-05-24
申请号：US12950508
申请日：2010-11-19
申请人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
发明人： Wagdi W. Abadeer , Cathryn J. Christiansen , John A. Fifield , Dimitris P. Ioannou , Tom C. Lee , Lilian Kamal
IPC分类号： G01K7/16
CPC分类号： G01K7/16
摘要： A system and a method for measuring temperature within an operating circuit use a Wheatstone bridge within a temperature sensing circuit. One of the resistors in the Wheatstone bridge is a thermally sensitive resistive material layer within the operating circuit. The other three resistors are thermally isolated from the operating circuit. Particular configurations of NFET and PFET devices are used to provide enhanced measurement sensitivity within the temperature sensing circuit that includes the Wheatstone bridge.
摘要翻译：用于测量操作电路内的温度的系统和方法使用温度感测电路内的惠斯通电桥。惠斯通电桥中的一个电阻器是操作电路内的热敏电阻材料层。其他三个电阻器与工作电路热绝缘。 NFET和PFET器件的特殊配置用于在包括惠斯通电桥的温度检测电路中提供增强的测量灵敏度。

3. 发明授权

US07873921B2 Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal 有权
标题翻译：集成电路中的电压检测电路的结构和产生触发标志信号的方法
公开(公告)号：US07873921B2
公开(公告)日：2011-01-18
申请号：US11948308
申请日：2007-11-30
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Albert M. Chu , John A. Fifield
IPC分类号： G06F17/50 , H03L7/00
CPC分类号： G06F17/5063 , G06F2217/78
摘要： A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
摘要翻译：一种用于集成电路的设计结构，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

4. 发明授权

US07825469B2 Threshold voltage compensation for pixel design of CMOS image sensors 有权
标题翻译： CMOS图像传感器的像素设计阈值电压补偿
公开(公告)号：US07825469B2
公开(公告)日：2010-11-02
申请号：US11850488
申请日：2007-09-05
申请人： Wagdi W. Abadeer , John A. Fifield
发明人： Wagdi W. Abadeer , John A. Fifield
IPC分类号： H01L29/72
CPC分类号： H04N5/374 , H04N5/365 , H04N5/3651 , H04N5/378
摘要： The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor.
摘要翻译：本公开涉及一种CMOS有源像素传感器，其补偿其中包含的源极跟随器的阈值电压的变化。根据实施例的结构包括：复制源极跟随器晶体管; 用于在所述复制源跟随器晶体管中产生电流的系统，使得所述复制源极跟随器的栅极 - 源极电压基本上等于所述复制源极跟随器的阈值电压; 以及电流镜，用于以与复制源极跟随器晶体管相同的电流密度偏置隔离源跟随器晶体管。

5. 发明授权

US07814449B2 Design structure for multiple source-single drain field effect semiconductor device and circuit 有权
标题翻译：多源单源漏极场效应半导体器件和电路的设计结构
公开(公告)号：US07814449B2
公开(公告)日：2010-10-12
申请号：US11873515
申请日：2007-10-17
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.
摘要翻译：公开了具有多个源极区域的可变延迟场效应晶体管（FET）的设计结构的实施例，其可被单独地和选择性地偏置以提供到单个漏极区域的电连接。延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

6. 发明授权

US07763531B2 Method and structure to process thick and thin fins and variable fin to fin spacing 有权
标题翻译：处理厚薄翅片和可变翅片翅片间距的方法和结构
公开(公告)号：US07763531B2
公开(公告)日：2010-07-27
申请号：US11846544
申请日：2007-08-29
申请人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthler, Jr. , Jed H. Rankin , William R. Tonti
发明人： Wagdi W. Abadeer , Jeffrey S. Brown , Kiran V. Chatty , Robert J. Gauthler, Jr. , Jed H. Rankin , William R. Tonti
IPC分类号： H01L21/425
CPC分类号： B07C5/344 , G01R31/2831
摘要： The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.
摘要翻译：本公开描述了在同一衬底上具有多个半导体鳍片的集成电路，其具有不同的宽度和可变间隔。形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET。

7. 发明授权

US07700428B2 Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory 失效
标题翻译：制造用作非易失性随机存取存储器中的存储器单元的器件结构的方法
公开(公告)号：US07700428B2
公开(公告)日：2010-04-20
申请号：US12117950
申请日：2008-05-09
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier , Jed H. Rankin , Yun Shi , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , H01L27/1203 , H01L29/66825
摘要： Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.
摘要翻译：制造用作非易失性随机存取存储器中的存储单元的器件结构的方法。该方法包括在绝缘层上形成具有分开且并置的关系的第一和第二半导体本体，掺杂第一半导体本体以形成源极和漏极，并且部分地移除第二半导体本体以限定邻近第一半导体体的通道。该方法还包括在第一半导体本体的沟道与浮栅之间形成第一电介质层，在浮置栅电极的顶表面上形成第二电介质层，在第二电介质层上形成控制栅电极，与浮栅电极配合，以控制第一半导体体的沟道中的载流子流动。

8. 发明申请

US20100041202A1 Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures 有权
标题翻译：形成后端电阻半导体结构的方法
公开(公告)号：US20100041202A1
公开(公告)日：2010-02-18
申请号：US12191633
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L21/76816 , H01L23/5226 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。覆盖第一金属线的第二电介质层的一部分使用光致抗蚀剂凹陷，第二金属线作为蚀刻掩模。在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

9. 发明申请

US20100019816A1 MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES 失效
标题翻译：具有标准场效应晶体管结构的微相调节和微相调节混频器电路
公开(公告)号：US20100019816A1
公开(公告)日：2010-01-28
申请号：US12573910
申请日：2009-10-06
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03K5/13
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译：这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。这些电路包括连接在输入和输出节点之间的可变延迟器件。该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过门和输出扩散区域并联连接到输出节点。当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

10. 发明申请

US20090243733A1 DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF 有权
标题翻译：用于变换输入电压以获得输入和输出功能与系统之间的线性的设计结构及其方法
公开(公告)号：US20090243733A1
公开(公告)日：2009-10-01
申请号：US12057686
申请日：2008-03-28
申请人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
发明人： Wagdi W. Abadeer , John A. Fifield , Stephen D. Wyatt
IPC分类号： H03L7/00
CPC分类号： H03L7/099
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括用于确定输入电压对输出频率响应的非线性特性的第一结构，第一设计结构提供与输入电压的基于隧道的电流关系。还公开了一种实现这种结构的系统和方法。

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