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1. 发明授权

US08405751B2 Image sensor pixel structure employing a shared floating diffusion 有权
标题翻译：采用共享浮动扩散的图像传感器像素结构
公开(公告)号：US08405751B2
公开(公告)日：2013-03-26
申请号：US12534427
申请日：2009-08-03
申请人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
发明人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
IPC分类号： H04N5/335
CPC分类号： H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37457
摘要： A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
摘要翻译：图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

2. 发明申请

US20110025892A1 IMAGE SENSOR PIXEL STRUCTURE EMPLOYING A SHARED FLOATING DIFFUSION 有权
标题翻译：图像传感器像素结构采用共享浮动扩展
公开(公告)号：US20110025892A1
公开(公告)日：2011-02-03
申请号：US12534427
申请日：2009-08-03
申请人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
发明人： Jason D. Hibbeler , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel
IPC分类号： H04N5/335 , H01L31/112 , G06F17/50
CPC分类号： H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37457
摘要： A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.
摘要翻译：图像传感器的像素结构包括具有共面且相邻的半导体表面的半导体材料部分，包括四个光电二极管，四个沟道区域和公共的浮动扩散区域。四个通道区域中的每一个直接邻接四个光电二极管和公共浮动扩散区域中的一个。四个光电二极管位于四个不同的象限内，如使用通过公共浮动扩散区域内的点作为中心轴的垂直线所限定的。公共浮动扩散区域，复位栅极晶体管，源极跟随器晶体管和行选择晶体管位于四个不同的象限内，如使用通过一个光电二极管内的点作为轴的垂直线所限定的。

3. 发明授权

US07752580B2 Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique 有权
标题翻译：基于使用开放确定性测序技术选择的样本窗口来分析集成电路的方法和系统
公开(公告)号：US07752580B2
公开(公告)日：2010-07-06
申请号：US11828728
申请日：2007-07-26
申请人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
发明人： Sarah C. Braasch , Jason D. Hibbeler , Rouwaida N. Kanj , Daniel N. Maynard , Sani R. Nassif , Evanthia Papadopoulou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.
摘要翻译：这里公开的是用于分析集成电路以确定该集成电路中的特定属性（即，物理或电气特性）的值的系统和相关方法的实施例。在实施例中，使用开放确定性测序技术来选择表示集成电路布局中的样本窗口中心的点序列。然后，为每个采样窗口确定特定属性的值，并累积结果，以推断整个集成电路布局的该特定属性的总体值。这种测序技术具有允许添加附加样品窗口和/或改变窗口的尺寸和形状而不妨碍样品质量的优点。

4. 发明授权

US07703061B2 IC design modeling allowing dimension-dependent rule checking 失效
标题翻译： IC设计建模允许维度依赖的规则检查
公开(公告)号：US07703061B2
公开(公告)日：2010-04-20
申请号：US12186769
申请日：2008-08-06
申请人： Evanthia Papadopoulou , Daniel N. Maynard
发明人： Evanthia Papadopoulou , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.
摘要翻译：一种用于对IC设计进行建模的方法，系统和程序产品，以一致的方式包括诸如局部宽度和IC形状间隔的尺寸。特别地，本发明使用Voronoi图的核心部分将形状的边缘划分成间隔，并且为每个间隔分配至少一个维度，例如局部宽度和间隔。尺寸分配可以作为针对宽度和间距设置的任何期望的定义，例如数值或连续尺寸依赖的设计规则。设计规则检查以尺寸为依据的间距规则，以宽度和间距的任意功能形式给出是可能的。本发明的应用可以在VLSI形状的宽度和间距例如相对于单个边缘，相邻边缘，相邻形状和/或针对IC设计的多于一个层中的边缘发挥作用的任何地方进行。

5. 发明申请

US20090031265A1 IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING 失效
公开(公告)号：US20090031265A1
公开(公告)日：2009-01-29
申请号：US12186764
申请日：2008-08-06
申请人： Evanthia Papadopoulou , Daniel N. Maynard
发明人： Evanthia Papadopoulou , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

6. 发明申请

US20080232675A1 SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 失效
标题翻译：集成电路系统缺陷的搜索与分析系统
公开(公告)号：US20080232675A1
公开(公告)日：2008-09-25
申请号：US12132710
申请日：2008-06-04
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

7. 发明授权

US07404174B2 method for generating a set of test patterns for an optical proximity correction algorithm 有权
标题翻译：用于生成用于光学邻近校正算法的一组测试图案的方法
公开(公告)号：US07404174B2
公开(公告)日：2008-07-22
申请号：US10710648
申请日：2004-07-27
申请人： David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
摘要翻译：一种合成布局图案以测试光学邻近校正算法的方法。该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

8. 发明申请

US20070294648A1 IC Layout Optimization To Improve Yield 失效
标题翻译： IC布局优化提高产量
公开(公告)号：US20070294648A1
公开(公告)日：2007-12-20
申请号：US11424922
申请日：2006-06-19
申请人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Faye D. Baker , Albert M. Chu , Michael S. Gray , Jason Hibbeler , Daniel N. Maynard , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.
摘要翻译：一种用于优化集成电路设计以提高制造产量的方法和服务。本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。确定关键区域的方法包括通用运行，几何映射和Voronoi图。优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

9. 发明授权

US06823496B2 Physical design characterization system 有权
标题翻译：物理设计表征系统
公开(公告)号：US06823496B2
公开(公告)日：2004-11-23
申请号：US10063427
申请日：2002-04-23
申请人： Bette L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
发明人： Bette L. Bergman Reuter , Mitchell R. DeHond , William C. Leipold , Daniel N. Maynard , Brian D. Pfeifer , David C. Reynolds , Reginald B. Wilcox, Jr.
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.
摘要翻译：用于在芯片设计数据中定位和定义分离到特定几何形状或形状配置的过程敏感点的系统，方法和介质。一旦确定了系统过程敏感站点，就会通过设计检查器对物理设计数据进行编码和执行3D设计检查台。产生目标匹配形状并将其嵌入到设计数据中。过程敏感站点的图片，地图和坐标生成并发送到网站库以供参考。

10. 发明授权

US5636133A Efficient generation of fill shapes for chips and packages 失效
标题翻译：有效地生成芯片和封装的填充形状
公开(公告)号：US5636133A
公开(公告)日：1997-06-03
申请号：US445447
申请日：1995-05-19
申请人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
发明人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.
摘要翻译：修改芯片或封装设计的有效方法允许创建小形状而不会过度扩展设计数据。计算机程序采用计算机数据文件中的物理设计，并生成已添加填充形状的设计的修改版本。随后，当改进的设计被处理时，所得到的半导体芯片或封装将包含所添加的填充形状的物理图像，具有使局部图案密度更均匀并因此减少特征尺寸和形状的工艺引起的变化的效果。

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