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    • 1. 发明授权
      US08448124B2 Post timing layout modification for performance 失效
    • Post timing layout modification for performance
    • 发布时序布局修改的性能
    • US08448124B2
    • 2013-05-21
    • US13236977
    • 2011-09-20
    • Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
    • Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
    • G06F17/50 , G06F9/455
    • G06F17/5068 , G06F2217/84
    • A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.
    • 提供了一种用于性能的后期时序布局修改的机制。 该机制基于路径级别的时序分析，选择性地应用布局修改。 该机制仅将压力应用于处于设置关键路径的晶体管，而不对保持关键路径中的晶体管施加压力。 该机制可以使用施加应力以提高晶体管在设置关键路径中的性能的方法，只要该应力不会改善保持关键路径中的相邻晶体管的性能即可。 在一些情况下，该机制可以施加应力以改善设置关键路径中的晶体管的性能，同时降低保持关键路径中的晶体管的性能。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US08302062B2 Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization 有权
    • Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization
    • 在分层电路布局优化中获得可行整数解的方法
    • US08302062B2
    • 2012-10-30
    • US12712880
    • 2010-02-25
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • G06F17/50
    • G06F17/5068
    • An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
    • 描述了在分层电路布局优化中获得可行整数解的方法。 在一个实施例中，接收分级电路布局和接地规则文件作为输入。 分层电路布局中的约束被表示为原始的整数线性规划问题。 通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。 解决了松弛的线性规划问题，以获得线性规划解决方案。 然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。 接下来，确定所有变量是否四舍五入为整数值。 通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。 响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US07761818B2 Obtaining a feasible integer solution in a hierarchical circuit layout optimization 失效
    • Obtaining a feasible integer solution in a hierarchical circuit layout optimization
    • 在分层电路布局优化中获得可行的整数解
    • US07761818B2
    • 2010-07-20
    • US11782706
    • 2007-07-25
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • G06F17/50
    • G06F17/5068
    • An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
    • 描述了在分层电路布局优化中获得可行整数解的方法。 在一个实施例中，接收分级电路布局和接地规则文件作为输入。 分层电路布局中的约束被表示为原始的整数线性规划问题。 通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。 解决了松弛的线性规划问题，以获得线性规划解决方案。 来自松弛线性规划问题的变量子集根据线性规划解决方案舍入为整数值。 接下来，确定所有变量是否四舍五入为整数值。 通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。 响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明申请
      US20100153892A1 METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION 有权
    • METHODS TO OBTAIN A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION
    • 在分层电路布局优化中获得可行整数解的方法
    • US20100153892A1
    • 2010-06-17
    • US12712880
    • 2010-02-25
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • G06F17/50
    • G06F17/5068
    • An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. Variables are then clustered, and at least one variable from each cluster is rounded to an integer value according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
    • 描述了在分层电路布局优化中获得可行整数解的方法。 在一个实施例中，接收分级电路布局和接地规则文件作为输入。 分层电路布局中的约束被表示为原始的整数线性规划问题。 通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。 解决了松弛的线性规划问题，以获得线性规划解决方案。 然后将变量进行聚类，根据线性规划解决方案，每个集群中至少有一个变量将四舍五入为整数值。 接下来，确定所有变量是否四舍五入为整数值。 通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。 响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20090031259A1 OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION 失效
    • OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION
    • 在分层电路布局优化中获得可行的整数解
    • US20090031259A1
    • 2009-01-29
    • US11782706
    • 2007-07-25
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • G06F17/50
    • G06F17/5068
    • An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represented as an original integer linear programming problem. A relaxed linear programming problem is derived from the original integer linear programming problem by relaxing integer constraints and using relaxation variables on infeasible constraints. The relaxed linear programming problem is solved to obtain a linear programming solution. A subset of variables from the relaxed linear programming problem is rounded to integer values according to the linear programming solution. Next, it is determined whether all the variables are rounded to integer values. Unrounded variables are iterated back through the deriving of the integer linear programming problem, solving of the relaxed linear programming problem, and rounding of a subset of variables. A modified hierarchical circuit layout is generated in response to a determination that all the variables are rounded to integer values.
    • 描述了在分层电路布局优化中获得可行整数解的方法。 在一个实施例中，接收分级电路布局和接地规则文件作为输入。 分层电路布局中的约束被表示为原始的整数线性规划问题。 通过放松整数约束和对不可行约束使用松弛变量，从原始整数线性规划问题导出松弛的线性规划问题。 解决了松弛的线性规划问题，以获得线性规划解决方案。 来自松弛线性规划问题的变量子集根据线性规划解决方案舍入为整数值。 接下来，确定所有变量是否四舍五入为整数值。 通过导出整数线性规划问题，解决松弛线性规划问题以及变量子集的舍入来迭代未包围的变量。 响应于所有变量被舍入到整数值的确定而产生修改的分层电路布局。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明申请
      US20080172638A1 METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING 审中-公开
    • METHOD OF OPTIMIZING HIERARCHICAL VERY LARGE SCALE INTEGRATION (VLSI) DESIGN BY USE OF CLUSTER-BASED LOGIC CELL CLONING
    • 通过使用基于群集的逻辑单元克隆优化分层级非常大规模集成（VLSI）设计的方法
    • US20080172638A1
    • 2008-07-17
    • US11623122
    • 2007-01-15
    • Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
    • Michael S. Gray , David J. Hathaway , Jason D. Hibbeler , Robert F. Walker , Xin Yuan
    • G06F17/50
    • G06F17/5045
    • A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.
    • 通过使用基于簇的细胞克隆来优化分级超大规模集成（VLSI）设计的方法。 本发明的方法通过重新使用细胞来提供改善的产量或迁移，以减少至少一个重复使用的细胞的唯一实例的数量。 该方法对减少的克隆集合（即，簇）执行层次优化。 本公开的方法包括但不限于设置初始聚类参数的步骤; 从现有的重复使用的电池组装物理设计; 对于每个单元格类型，执行完全克隆操作以便创建一整套重复的单元格; 对于每个单元格类型，执行设计的全面优化; 对于每个单元类型，执行所有单元环境的分析并执行聚类操作; 并分析总体结果，以确定是否实现优化目标。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US08296706B2 Handling two-dimensional constraints in integrated circuit layout 有权
    • Handling two-dimensional constraints in integrated circuit layout
    • 处理集成电路布局中的二维约束
    • US08296706B2
    • 2012-10-23
    • US12767375
    • 2010-04-26
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • Michael S. Gray , Xiaoping Tang , Xin Yuan
    • G06F17/50
    • G06F17/5068
    • A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints; generating two-dimensional clusters including groups of the two-dimensional constraints; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters.
    • 公开了一种用于处理集成电路（IC）布局的布局优化中的多个约束的计算机实现的方法。 在一个实施例中，该方法包括构建表示多个约束的图; 标记所述多个约束中的二维约束; 生成包括二维约束的二维群集; 处理所述二维集群中的至少一个，所述处理包括找到所述至少一个二维集群中的所述二维约束的解; 重复对任何未处理的二维簇的处理，直到处理所有二维簇; 并且针对每个二维聚类采用解，以解决包括二维聚类的多个约束的至少一部分。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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