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    • 7. 发明授权
    • Method and apparatus for source synchronous data transfer
    • 源同步数据传输的方法和装置
    • US06178206B1
    • 2001-01-23
    • US09013479
    • 1998-01-26
    • Timothy W. KellyStephen S. PawlowskiKeith M. SelfJeffrey E. Smith
    • Timothy W. KellyStephen S. PawlowskiKeith M. SelfJeffrey E. Smith
    • H04L2500
    • H04L7/0331H04L7/0008
    • A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.
    • 提出了一种用于在两个或更多个组件之间传输数据的方法和装置。 数据信号与时钟信号(例如,总线)并行地发送,使得可以相对于时钟信号锁存数据信号。 例如,可以在双向时钟信号线上发送彼此异相180度的两个时钟信号,并且数据信号可以在数据信号线上发送,接收时钟和数据信号的组件可以锁存数据信号 在两个时钟信号中的任一个的每个从高到低的转换。 使用本发明的方法和装置,可以减少其他总线系统所看到的偏斜问题,这导致数据传输速率的增加。
    • 8. 发明授权
    • Multiple internal phase-locked loops for synchronization of chipset
components and subsystems operating at different frequencies
    • 用于同步芯片组件和不同频率工作的子系统的多个内部锁相环
    • US6047383A
    • 2000-04-04
    • US12479
    • 1998-01-23
    • Keith M. SelfJeffrey E. SmithKeng L. Wong
    • Keith M. SelfJeffrey E. SmithKeng L. Wong
    • G06F1/12
    • G06F1/12
    • Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit. The following steps are performed for each selected output pin coupled to provide a synchronized clock signal at the end of a propagation trace: a) determining an electrical length of the propagation trace; and b) providing a feedback trace from the output pin to a feedback pin of the corresponding PLL, wherein the feedback trace is a same electrical length as the propagation trace. A divided-by-n reference clock signal is then provided to at least one of the PLLs, wherein n is not equal to 1.
    • 描述了关于在不同频率下需要相对同步性的计算机系统组件和子系统的放置的宽松设计约束的方法和装置。 在一个实施例中,该装置包括形成在集成电路管芯上的第一锁相环(PLL)。 参考时钟信号引脚通过电长度L1的路径耦合到第一PLL,以将参考时钟信号传播到第一PLL。 第一PLL反馈引脚通过电长度L2的路径耦合到第一PLL,其中L1 APPROX L2。 该装置包括耦合到参考时钟信号引脚的可编程计数器,该可编程计数器向第一PLL提供划分的基准时钟信号。 在一个实施例中,该方法包括向驻留在同一集成电路中的多个PLL提供参考时钟信号的步骤。 至少一些PLL的输出耦合到集成电路的相应输出引脚。 对于耦合以在传播轨迹结束时提供同步时钟信号的每个选择的输出引脚执行以下步骤:a)确定传播轨迹的电长度; 以及b)提供从所述输出引脚到相应PLL的反馈引脚的反馈迹线,其中所述反馈迹线与所述传播迹线具有相同的电长度。 然后,将一个分频参考时钟信号提供给至少一个PLL,其中n不等于1。
    • 9. 发明授权
    • Analog compensation circuitry for integrated circuit input/output
circuitry
    • 用于集成电路输入/输出电路的模拟补偿电路
    • US06025792A
    • 2000-02-15
    • US12478
    • 1998-01-23
    • Jeffrey E. Smith
    • Jeffrey E. Smith
    • G05F3/24H03K19/003H03M1/12
    • G05F3/247G05F3/245H03K19/00384
    • An analog compensation circuit for providing process/voltage/temperature (PVT) bias compensation signals for input/output (I/O) circuitry within an integrated circuit includes a first current source coupled to a first node. A first load coupled to the first current source and a second node provides a first reference voltage. A voltage divider coupled between the first and second nodes provides a current source bias voltage to the first current source. A differential amplifier generates a first bias compensation signal as feedback for the first current source in accordance with the difference between the first reference voltage and a second reference voltage. With the addition of logic level bias converters, the compensation circuitry is capable of providing bias compensation signals to multiple logic families. The bias compensation signals can be applied to current sources used to control the functioning of integrated circuit I/O circuitry so that the I/O circuitry operates substantially independently of PVT variations.
    • 用于为集成电路内的输入/输出(I / O)电路提供过程/电压/温度(PVT)偏置补偿信号的模拟补偿电路包括耦合到第一节点的第一电流源。 耦合到第一电流源和第二节点的第一负载提供第一参考电压。 耦合在第一和第二节点之间的分压器为第一电流源提供电流源偏置电压。 差分放大器根据第一参考电压和第二参考电压之间的差产生作为第一电流源的反馈的第一偏置补偿信号。 通过增加逻辑电平偏置转换器,补偿电路能够向多个逻辑系列提供偏置补偿信号。 偏置补偿信号可以应用于用于控制集成电路I / O电路的功能的电流源,使得I / O电路基本上独立于PVT变化操作。