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1. 发明授权

US07550994B1 Programmable logic device with on-chip nonvolatile user memory 有权
标题翻译：具有片上非易失性用户存储器的可编程逻辑器件
公开(公告)号：US07550994B1
公开(公告)日：2009-06-23
申请号：US11668325
申请日：2007-01-29
申请人： Rafael C. Camarota , Thomas H. White
发明人： Rafael C. Camarota , Thomas H. White
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17772 , G11C7/20 , H03K19/1776
摘要： A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.
摘要翻译：可编程逻辑集成电路具有由可编程逻辑使用的用户可访问的非易失性存储器。在具体实施例中，可编程逻辑集成电路具有可编程逻辑阵列部分和非易失性存储器阵列部分。非易失性存储器阵列部分被分离成引导数据部分和用户数据分区。引导数据分区保存用于在上电时配置可编程逻辑部分的数据，并且用户数据分区由可编程逻辑使用。用户可以从用户数据分区存储和检索数据。内置振荡器可以从非易失性存储器部分可编程地连接到PLD部分。

2. 发明授权

US09026872B2 Flexible sized die for use in multi-die integrated circuit 有权
标题翻译：适用于多芯片集成电路的灵活尺寸的裸片
公开(公告)号：US09026872B2
公开(公告)日：2015-05-05
申请号：US13587778
申请日：2012-08-16
申请人： Rafael C. Camarota
发明人： Rafael C. Camarota
IPC分类号： G01R31/28 , H01L21/66 , H01L23/14 , H01L25/065 , H01L23/498 , H01L21/78
CPC分类号： G01R31/28 , H01L21/78 , H01L22/32 , H01L23/145 , H01L23/147 , H01L23/49827 , H01L25/0652 , H01L25/0655 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/14 , H01L2924/14253 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434 , H01L2924/1435 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/0105
摘要： An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.
摘要翻译：集成电路（IC）结构可以包括第一管芯和第二管芯。第二模具可以包括第一基座单元和第二基座单元。第一基座单元和第二基座单元中的每一个是独立的，并且在第二模具内的第一基座单元和第二基座单元之间没有信号通过。 IC结构可以包括插入器。插入器包括将第一管芯耦合到第一基底单元的第一多个管芯间线，将第一管芯连接到第二基底单元的第二多个管芯间线和将第一管芯连接到第二基底单元的第三多个管芯间线第一基座单元到第二基座单元。

3. 发明授权

US06294925B1 Programmable logic device 有权
标题翻译：可编程逻辑器件
公开(公告)号：US06294925B1
公开(公告)日：2001-09-25
申请号：US09440460
申请日：1999-11-15
申请人： Albert Chan , Ju Shen , Cyrus Y. Tsui , Rafael C. Camarota
发明人： Albert Chan , Ju Shen , Cyrus Y. Tsui , Rafael C. Camarota
IPC分类号： H03K19177
CPC分类号： H03K19/17728 , H03K17/163
摘要： An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits. This invention may be used to delay output signals which are not time-critical, allowing fast switching of the limited number of time-critical macrocell output signals.
摘要翻译：产生在时间上偏斜的输出信号的改进的可编程逻辑器件包括一组I / O单元和第一和第二逻辑电路。每个逻辑电路在耦合到至少一个I / O单元的相应输出线上产生逻辑输出信号。耦合到第一逻辑电路的输出线的第一延迟元件可编程地用于响应于第一延迟控制信号而相对于第二逻辑电路的输出信号延迟第一逻辑电路的输出信号。耦合到第二逻辑电路的输出线的第二延迟元件可编程地可操作地响应于第二延迟控制信号而延迟第二逻辑电路相对于第一逻辑电路的输出信号的输出信号。控制电路产生第一和第二延迟控制信号，以防止第一和第二逻辑电路的逻辑输出信号的同时切换。本发明可以用于延迟不是时间关键的输出信号，允许有限数量的时间关键的宏单元输出信号的快速切换。

4. 发明授权

US5218240A Programmable logic cell and array with bus repeaters 失效
标题翻译：具有总线中继器的可编程逻辑单元和阵列
公开(公告)号：US5218240A
公开(公告)日：1993-06-08
申请号：US935116
申请日：1992-08-25
申请人： Rafael C. Camarota , Frederick C. Furtek , Walford W. Ho , Edward H. Browder
发明人： Rafael C. Camarota , Frederick C. Furtek , Walford W. Ho , Edward H. Browder
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H03K19/17792
摘要： A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.
摘要翻译：一种包括单元和总线网络的可编程逻辑阵列，其中单元被布置在行和列的二维矩阵中，并且由总线网络互连。细胞还通过细胞与其四个最近邻居之间的直接连接的二维阵列相互连接，一个在其左侧（或向西部），一个在其右侧（或向东部），一个在其上方（或到北方）和其中一个（或南部）。每个单元包括八个输入，八个输出，用于将八个输入复用到两个引线上的装置，以及响应于两个引线上的信号而工作以产生施加到八个输出的输出信号的逻辑装置。总线网络包括用于阵列的每行和列的本地，转向和快速总线以及用于分配给定行或列的所述总线以形成总线段的中继器装置。总线网络提供将数据传输到阵列的单元，而不使用单元作为单独的电线。

5. 发明授权

US06229336B1 Programmable integrated circuit device with slew control and skew control 有权
标题翻译：可编程集成电路器件，具有摆幅控制和偏移控制
公开(公告)号：US06229336B1
公开(公告)日：2001-05-08
申请号：US09186917
申请日：1998-11-06
申请人： Bradley Felton , Albert Chan , Ju Shen , Cyrus Y. Tsui , Rafael C. Camarota
发明人： Bradley Felton , Albert Chan , Ju Shen , Cyrus Y. Tsui , Rafael C. Camarota
IPC分类号： H03K19173
CPC分类号： H03K17/163 , H03K19/17744 , H03K19/17792
摘要： A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.
摘要翻译：可编程集成电路装置包括多个输出端子，每个输出端子用于发送相应的输出信号。定时控制电路连接到输出端子。定时控制电路可操作以延迟每个输出端上的输出信号，并且还可操作以控制每个输出端上的输出信号的转换速率。

6. 发明授权

US5805503A Non-disruptive randomly addressable memory system 失效
标题翻译：无中断随机可寻址内存系统
公开(公告)号：US5805503A
公开(公告)日：1998-09-08
申请号：US582516
申请日：1996-01-03
申请人： Rafael C. Camarota
发明人： Rafael C. Camarota
IPC分类号： G11C11/41 , G11C11/405 , G11C13/00 , H03K19/177
CPC分类号： H03K19/17752 , H03K19/17704 , H03K19/17756 , H03K19/1776
摘要： An apparatus and method for reprogramming a reconfigurable-logic array is provided whereby a portion of the array can be reconfigured without disrupting the operation of the entire array. Avoiding total disruption of array operation typically requires that the configuration control signals, which determine the configuration of the array, remain substantially non-disrupted during a reprogramming operation. In one embodiment, the reprogramming operates by unique decoding in which an electrical path is established only between the particular storage elements being reprogrammed, thereby avoiding disruption of the configuration control signals provided by other storage elements. In other embodiments, buffers and/or read-modify-write techniques are used to minimize disruption of configuration control signals of storage elements not being reprogrammed.
摘要翻译：提供了一种用于重新编程可重构逻辑阵列的装置和方法，其中阵列的一部分可以被重新配置而不中断整个阵列的操作。避免阵列操作的完全中断通常要求在重新编程操作期间确定阵列的配置的配置控制信号基本上不中断。在一个实施例中，重编程通过唯一解码操作，其中仅在被重新编程的特定存储元件之间建立电路径，从而避免由其他存储元件提供的配置控制信号的中断。在其他实施例中，使用缓冲器和/或读 - 修改 - 写入技术来最小化不被重新编程的存储元件的配置控制信号的中断。

7. 发明授权

US5298805A Versatile and efficient cell-to-local bus interface in a configurable logic array 失效
标题翻译：可配置逻辑阵列中通用且高效的单元到本地总线接口
公开(公告)号：US5298805A
公开(公告)日：1994-03-29
申请号：US44921
申请日：1993-04-08
申请人： Tim Garverick , Jim Sutherland , Sanjay Popli , Venkata Alturi , Arthur Smith, Jr. , Scott Pickett , David Hawley , Shao-Pin Chen , Shankar Moni , Benjamin S. Ting , Rafael C. Camarota , Shin-Mann Day , Frederick Furtek
发明人： Tim Garverick , Jim Sutherland , Sanjay Popli , Venkata Alturi , Arthur Smith, Jr. , Scott Pickett , David Hawley , Shao-Pin Chen , Shankar Moni , Benjamin S. Ting , Rafael C. Camarota , Shin-Mann Day , Frederick Furtek
IPC分类号： H03K17/22 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K17/223 , H03K19/00361 , H03K19/1736 , H03K19/17704 , H03K19/17736
摘要： A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.
摘要翻译：用于可编程逻辑阵列的低晶体管计数可编程总线资源允许使用总线资源作为阵列中的单元的输入或输出，并且允许不同总线之间的连接，而不影响电池的正常使用。总线资源允许在单元之间有效地路由信号，并且对称地允许使用单元和总线的组合构建的逻辑宏的旋转。

8. 发明授权

US4910712A Memory cell with a plurality of pass gates 失效
标题翻译：具有多个通孔的存储单元
公开(公告)号：US4910712A
公开(公告)日：1990-03-20
申请号：US157632
申请日：1988-02-18
申请人： Rafael C. Camarota , H. William Wang
发明人： Rafael C. Camarota , H. William Wang
IPC分类号： G11C8/16 , H03K3/356 , H03K19/0944
CPC分类号： G11C8/16 , H03K19/09441 , H03K3/356052
摘要： Disclosed is a memory cell which includes a plurality of pass gates in the read word and write word lines. The pass gates are connected in series and each pass gate is controlled by a separate line, namely, by a write word line or a read word line. By use of two or more pass gates in this manner, logical functions, such as logical AND functions are performed within the memory cell.
摘要翻译：公开了一种存储单元，其包括读取字中的多个通过门和写入字线。传输门串联连接，每个通道由单独的一行控制，即通过写字线或读字线控制。通过以这种方式使用两个或更多个传递门，在存储器单元内执行诸如逻辑与功能的逻辑功能。

9. 发明授权

US07276935B1 Input buffer with selectable threshold and hysteresis option 有权
标题翻译：具有可选阈值和滞后选项的输入缓冲器
公开(公告)号：US07276935B1
公开(公告)日：2007-10-02
申请号：US11340408
申请日：2006-01-25
申请人： Rafael C. Camarota
发明人： Rafael C. Camarota
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17744 , H03K19/17788
摘要： An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.
摘要翻译：输入缓冲器可配置为用作具有单个切换阈值的标准缓冲器，可选择为至少两个不同切换阈值中的一个，或用作具有迟滞的施密特触发电路，其使用至少两个切换阈值至少两个不同的切换阈值。集成电路可以是可编程逻辑器件（PLD）或现场可编程门阵列（FPGA），但是在其他实施例中，集成电路可以是其他类型的器件，例如微处理器，ASIC或存储器。

10. 发明授权

US06418045B1 Efficient and robust random access memory cell suitable for programmable logic configuration control 有权
公开(公告)号：US06418045B1
公开(公告)日：2002-07-09
申请号：US09896406
申请日：2001-06-28
申请人： Rafael C. Camarota
发明人： Rafael C. Camarota
IPC分类号： G11C1100
摘要： For a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation comprises steps of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak passgate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches. A memory cell with such a weak passgate and operating characteristics is taught, a configuration memory using such cells, and a Programmable Logic Array with such a configuration memory.

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