专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5298805A Versatile and efficient cell-to-local bus interface in a configurable logic array 失效
标题翻译：可配置逻辑阵列中通用且高效的单元到本地总线接口
公开(公告)号：US5298805A
公开(公告)日：1994-03-29
申请号：US44921
申请日：1993-04-08
申请人： Tim Garverick , Jim Sutherland , Sanjay Popli , Venkata Alturi , Arthur Smith, Jr. , Scott Pickett , David Hawley , Shao-Pin Chen , Shankar Moni , Benjamin S. Ting , Rafael C. Camarota , Shin-Mann Day , Frederick Furtek
发明人： Tim Garverick , Jim Sutherland , Sanjay Popli , Venkata Alturi , Arthur Smith, Jr. , Scott Pickett , David Hawley , Shao-Pin Chen , Shankar Moni , Benjamin S. Ting , Rafael C. Camarota , Shin-Mann Day , Frederick Furtek
IPC分类号： H03K17/22 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K17/223 , H03K19/00361 , H03K19/1736 , H03K19/17704 , H03K19/17736
摘要： A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.
摘要翻译：用于可编程逻辑阵列的低晶体管计数可编程总线资源允许使用总线资源作为阵列中的单元的输入或输出，并且允许不同总线之间的连接，而不影响电池的正常使用。总线资源允许在单元之间有效地路由信号，并且对称地允许使用单元和总线的组合构建的逻辑宏的旋转。

2. 发明授权

US5319255A Power up detect circuit for configurable logic array 失效
标题翻译：上电检测电路可配置逻辑阵列
公开(公告)号：US5319255A
公开(公告)日：1994-06-07
申请号：US15412
申请日：1993-02-09
申请人： Tim Garverick , Shao-Pin Chen , Rafael C. Camarota
发明人： Tim Garverick , Shao-Pin Chen , Rafael C. Camarota
IPC分类号： H03K17/22 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/223 , H03K19/00361 , H03K19/1736 , H03K19/17704 , H03K19/17728
摘要： The present invention provides power up detect circuit for generating a reset signal for a logic circuit that includes N-channel transistors having a threshold value Vnth and P-channel transistors having a threshold value Vpth. The power-up detect circuit includes comparison means having first and second inputs; clamping means for clamping the first comparison means input at X*Vnth above ground potential; and monitoring means connected to the second comparison means input and responsive to ramp up of a power supply voltage for holding the second comparison means input at X*Vpth less than the power supply voltage whereby the comparison means output switches from an inactive state to an active state when the power supply to ground potential reaches (X*Vnth)+(X*Vpth). The power up detect circuit further includes hysteresis means connected between the comparison means output and the second comparison means input and responsive to the power supply for preventing the comparison means output from switching from the active state to the machine state if the power supply voltage remains above (X*Vnth+Y*Vpth)-(WVnth+ZVpth), where 0
摘要翻译：本发明提供了一种用于产生包括具有阈值Vnth的N沟道晶体管和具有阈值Vpth的P沟道晶体管的逻辑电路的复位信号的上电检测电路。上电检测电路包括具有第一和第二输入的比较装置; 钳位装置，用于将第一比较装置的输入钳位在地电位以上X * Vnth处; 以及连接到第二比较装置输入的监视装置，并且响应于提供电源电压的斜坡上升，以保持第二比较装置输入的电压低于电源电压的X * Vpth，由此比较装置输出从非活动状态切换到活动状态当地电位达到（X * Vnth）+（X * Vpth）时的状态。上电检测电路还包括连接在比较装置输出和第二比较装置输入之间的迟滞装置，并且响应于电源，如果电源电压保持高于，则防止比较装置输出从活动状态切换到机器状态（X * Vnth + Y * Vpth） - （WVnth + ZVpth），其中0

3. 发明授权

US5341040A High performance output buffer with reduced ground bounce 失效
标题翻译：高性能输出缓冲器，减少地面反弹
公开(公告)号：US5341040A
公开(公告)日：1994-08-23
申请号：US15371
申请日：1993-02-09
申请人： Tim Garverick , Shao-Pin Chen , Rafael C. Camarota
发明人： Tim Garverick , Shao-Pin Chen , Rafael C. Camarota
IPC分类号： H03K17/22 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/223 , H03K19/00361 , H03K19/1736 , H03K19/17704 , H03K19/17728
摘要： The present invention provides circuitry for compensating the slew rate of an output buffer so as to reduce the magnitude of the variation in slew rate and ground bounce due to temperature and processing variations. The circuitry includes structure at the gate of each transistor that supplies or sinks current to charge or discharge capacitance at the output buffer output that slows down the turn on of the output transistors as temperature or process shifts in a way that would tend to increase the current carrying capability of the output transistor. The structure includes a transmission gate having its source connected to the gate of the output transistor, its drain connected to a capacitor, and its gate connected such that it is conducting.
摘要翻译：本发明提供用于补偿输出缓冲器的转换速率的电路，以便降低由于温度和处理变化引起的转换速率和地面反弹的变化的幅度。该电路包括在每个晶体管的栅极处的结构，其提供或吸收电流以在输出缓冲器输出端对电容进行充电或放电，以减慢输出晶体管的导通，因为温度或过程以倾向于增加电流的方式移动输出晶体管的承载能力。该结构包括其源极连接到输出晶体管的栅极的传输栅极，其漏极连接到电容器，并且其栅极连接使得其导通。

4. 发明授权

US5317209A Dynamic three-state bussing capability in a configurable logic array 失效
标题翻译：可配置逻辑阵列中的动态三态总线功能
公开(公告)号：US5317209A
公开(公告)日：1994-05-31
申请号：US14464
申请日：1993-02-05
申请人： Tim Garverick , Rafael C. Camarota
发明人： Tim Garverick , Rafael C. Camarota
IPC分类号： H03K17/22 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/223 , H03K19/00361 , H03K19/1736 , H03K19/17704 , H03K19/17728
摘要： The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of rows of logic cells and a plurality of columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array also includes means for configuring the array such that any logic cell A in the array can write to a local bus which can be linked through the array's bussing network so that logic cell A can be read by any other logic cell B; correspondingly, logic cell B can write to a local bus which is linked through the same components such that data written by logic cell B can be read by logic cell A. Whether a logic element is reading from or writing to a local bus in controlled by a logic function created in the array. The configuration capability is due to means for placing the bus drivers in a high impedance state, means for bidirectional bussing capability due to extra passgates in the array repeaters, and means for connecting horizontal busses to vertical busses through the use of a core cell to bus interface.
摘要翻译：本发明提供了一种可配置逻辑阵列，其包括以矩阵形式布置的多个可单独配置的逻辑单元，其包括多行逻辑单元和多列逻辑单元。该阵列还包括至少一个水平对准的本地总线，其运行在相邻的逻辑单元行之间，相邻行中的逻辑单元可连接到其上，以及至少一个垂直对齐的本地总线，其运行在逻辑单元的相邻列之间，相邻列可连接到其上。阵列还包括用于配置阵列的装置，使得阵列中的任何逻辑单元A可以写入可以通过阵列的总线网络链接的本地总线，使得逻辑单元A可以被任何其他逻辑单元B读取; 相应地，逻辑单元B可以写入通过相同组件链接的局部总线，使得由逻辑单元B写入的数据可由逻辑单元A读取。逻辑单元是否从本地总线读取或写入到由在数组中创建的逻辑函数。配置能力是由于将总线驱动器置于高阻抗状态的手段，由于阵列中继器中额外的通路，双向总线能力的装置，以及通过使用核心单元到总线将水平总线连接到垂直总线的装置接口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式