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1. 发明授权

US06245672B1 Method of forming diffusion barriers for copper metallization in integrated cirucits 有权
标题翻译：在集成的铁芯中形成铜金属化的扩散阻挡层的方法
公开(公告)号：US06245672B1
公开(公告)日：2001-06-12
申请号：US09177412
申请日：1998-10-23
申请人： Qi-Zhong Hong , Wei-Yung Hsu , Jiong-Ping Lu , Robert H. Havemann
发明人： Qi-Zhong Hong , Wei-Yung Hsu , Jiong-Ping Lu , Robert H. Havemann
IPC分类号： H01L214763
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76855
摘要： An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate (9), which is typically clad with a metal silicide film (12) formed by way of direct react silicidation. At contact locations (CT) at which the copper metallization (20, 32, 42) is to make contact to the doped region (7), a chemically-densified barrier layer (16, 30, 38) provides a diffusion barrier to the overlying copper metallization (20, 32, 42). The chemically-densified barrier layer (16, 30, 38) is formed by an anneal of the structure to react impurities (14, 28, 36) with the underlying refractory-metal-based film (12, 34); the impurities are introduced by way of wet chemistry, plasma bombardment, or from the ambient in which the structure is annealed.
摘要翻译：公开了一种包括铜金属化（20,32,42）的集成电路结构及其制造方法。该结构包括硅衬底（9）的掺杂区域（7），其通常用通过直接反应硅化形成的金属硅化物膜（12）包覆。在铜金属化层（20,32,42）将与掺杂区域（7）接触的接触位置（CT）处，化学致密化的势垒层（16,30,38）为覆盖层铜金属化（20,32,42）。化学致密化的阻挡层（16,30,38）通过该结构的退火形成，以使杂质（14,28,36）与下面的耐熔金属基膜（12,34）反应; 杂质通过湿化学，等离子体轰击或结构退火的环境引入。

2. 发明授权

US6077782A Method to improve the texture of aluminum metallization 失效
标题翻译：改善铝金属化质地的方法
公开(公告)号：US6077782A
公开(公告)日：2000-06-20
申请号：US23424
申请日：1998-02-13
申请人： Wei-Yung Hsu , Qi-Zhong Hong , Robert H. Havemann
发明人： Wei-Yung Hsu , Qi-Zhong Hong , Robert H. Havemann
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76814 , H01L21/76843 , H01L21/76862 , H01L21/76882 , H01L23/53223 , H01L2924/0002
摘要： A method to improve the texture of titanium and aluminum to reduce electromigration by controlling the deposition conditions and the texture of the substrates. Aluminum films can develop strong texture, when titanium is used underneath aluminum. However, to prevent the interaction between aluminum and titanium, a layer of TiN or other barrier is necessary. Fortunately, TiN has a similar atom arrangement on the plane as that of aluminum and titanium . Therefore, by controlling the orientation of titanium using a pre-sputter argon etch and low titanium deposition temperature, the texture of titanium can be transferred to TiN, and subsequently to aluminum.
摘要翻译：通过控制沉积条件和基板的质地，改善钛和铝的织构以减少电迁移的方法。当铝在铝下使用时，铝膜可以发展出强烈的<111>质感。然而，为了防止铝和钛之间的相互作用，需要一层TiN或其它屏障。幸运的是，TiN在<111>平面上具有与铝<111>和钛<002>相似的原子排列。因此，通过使用预溅射氩蚀刻和低钛沉积温度控制钛的取向，钛的织构可以转移到TiN，然后转移到铝。

3. 发明授权

US06355559B1 Passivation of inlaid metallization 有权
标题翻译：嵌入金属化钝化
公开(公告)号：US06355559B1
公开(公告)日：2002-03-12
申请号：US09706275
申请日：2000-11-03
申请人： Robert H. Havemann , Qi-Zhong Hong , Girish Dixit
发明人： Robert H. Havemann , Qi-Zhong Hong , Girish Dixit
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/76852 , H01L21/76856 , H01L21/76858 , H01L21/76886
摘要： A method for forming a metal interconnect having a self-aligned transition metal-nitride barrier (124). After the metal interconnect lines (118) are formed, a transition metal (120) is deposited over the surface of the metal interconnect lines (118) and reacted in to form a metal-compound (122). The metal-compound (122) is then annealed in a nitrogen ambient to form a barrier layer (114) at the surface of the metal interconnect lines (118).
摘要翻译：一种用于形成具有自对准过渡金属氮化物屏障（124）的金属互连的方法。在金属互连线（118）形成之后，过渡金属（120）沉积在金属互连线（118）的表面上并反应以形成金属化合物（122）。金属化合物（122）然后在氮气环境中退火以在金属互连线（118）的表面形成阻挡层（114）。

4. 发明授权

US5605724A Method of forming a metal conductor and diffusion layer 失效
标题翻译：形成金属导体和扩散层的方法
公开(公告)号：US5605724A
公开(公告)日：1997-02-25
申请号：US407353
申请日：1995-03-20
申请人： Qi-Zhong Hong , Robert H. Havemann
发明人： Qi-Zhong Hong , Robert H. Havemann
IPC分类号： C23C14/06 , C23C14/34 , C23C16/50 , H01L21/203 , H01L21/3205 , H01L21/768 , H01L23/52 , H05H1/00
CPC分类号： H01L21/76856 , H01L21/76843
摘要： A method for minimizing reaction between metal conductors and other metals to minimize change in sheet resistance of the conductors upon heat treatment which includes providing a substrate. The substrate is preferably one of a dielectric, a metal or a semiconductor. A metallic diffusion barrier layer, preferably one of TiN, TiW or TiWN and preferably having a thickness of from about 10 nanometers to about 100 nanometers, is deposited on the substrate, preferably by one of sputtering, electron beam evaporation or chemical vapor deposition. The exposed surface of the metallic diffusion barrier layer is treated with a plasma, preferably an oxygen plasma, a nitrous oxide plasma or a plasma of an oxygen-containing species. An electrical conductor, preferably one of aluminum, aluminum-metal alloys, copper or copper-metal alloys and preferably having a thickness of from about 100 nanometers to about 1200 nanometers, is then deposited on the plasma-treated surface of the metallic diffusion barrier layer. The layers can be formed as one of a blanket or continuous films over the substrate. The conductor can then be patterned.
摘要翻译：一种用于使金属导体和其它金属之间的反应最小化的方法，以使热处理时导体的薄层电阻变化最小化，包括提供基板。基板优选为电介质，金属或半导体中的一种。优选通过溅射，电子束蒸发或化学气相沉积中的一种沉积在金属扩散阻挡层上，优选TiN，TiW或TiWN中的一种，优选具有约10纳米至约100纳米的厚度。金属扩散阻挡层的暴露表面用等离子体，优选氧等离子体，一氧化二氮等离子体或含氧物质的等离子体进行处理。然后将电导体（优选铝，铝 - 金属合金，铜或铜 - 金属合金中的一种）优选地具有约100纳米至约1200纳米的厚度，然后沉积在金属扩散阻挡层的等离子体处理的表面上。这些层可以形成为衬底上的覆盖层或连续膜之一。然后可以对导体进行图案化。

5. 发明授权

US06358849B1 Integrated circuit interconnect and method 有权
标题翻译：集成电路互连和方法
公开(公告)号：US06358849B1
公开(公告)日：2002-03-19
申请号：US09467680
申请日：1999-12-21
申请人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
发明人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/31053 , H01L21/76224 , H01L21/76849 , H01L21/76856 , H01L21/76867
摘要： A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.
摘要翻译：一种双嵌入互连制造方法，在沟槽蚀刻中沟槽蚀刻和去除填充物之后，在通孔中使用临时填料。这在沟槽蚀刻期间通过底部保护提供。

6. 发明授权

US5668411A Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits 失效
标题翻译：用于最小化集成电路的金属化层之间的反应的扩散阻挡三层
公开(公告)号：US5668411A
公开(公告)日：1997-09-16
申请号：US685159
申请日：1996-07-23
申请人： Qi-Zhong Hong , Shin-Puu Jeng , Robert H. Havemann
发明人： Qi-Zhong Hong , Shin-Puu Jeng , Robert H. Havemann
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/78 , H01L21/44 , H01L29/43
CPC分类号： H01L21/76876 , H01L21/76841 , H01L23/5226 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , Y10S257/915
摘要： A diffusion barrier trilayer 42 is comprised of a bottom layer 44, a seed layer 46 and a top layer 48. The diffusion barrier trilayer 42 prevents reaction of metallization layer 26 with the top layer 48 upon heat treatment, resulting in improved sheet resistance and device speed.
摘要翻译：扩散阻挡三层42由底层44，种子层46和顶层48组成。扩散阻挡三层42防止金属化层26与顶层48在热处理时的反应，导致改善的薄层电阻和装置速度。

7. 发明授权

US06995439B1 Method of fabricating low dielectric constant dielectric films 失效
标题翻译：制备低介电常数介电膜的方法
公开(公告)号：US06995439B1
公开(公告)日：2006-02-07
申请号：US10803234
申请日：2004-03-17
申请人： Richard S. Hill , Willibrordus Gerardus Maria van den Hoek , Robert H. Havemann
发明人： Richard S. Hill , Willibrordus Gerardus Maria van den Hoek , Robert H. Havemann
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/7682 , H01L2221/1047
摘要： Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.
摘要翻译：通过在致密电介质的预先形成的层中引入小的垂直或柱状间隙来产生多孔电介质层。可以通过与用于在VLSI器件上形成金属线和其它特征的工艺不同的特殊工艺形成孔。此外，在特定层的平坦化处理已经完成之后可以产生柱状间隙。然后，在形成孔之后，通过沉积另一层材料来封盖它们。以这种方式，保护新的多孔层免于直接暴露于随后的平坦化工艺的压力。在替代实施例中，应用本文所述的工艺以将孔引入预成形的半导体层中以产生多孔半导体层。

8. 发明授权

US06365451B2 Transistor and method 有权
标题翻译：晶体管和方法
公开(公告)号：US06365451B2
公开(公告)日：2002-04-02
申请号：US09821602
申请日：2001-03-29
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L218238
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/1004 , H01L29/7322
摘要： A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.
摘要翻译：一种制造半导体器件和器件的方法。该器件通过提供具有导电材料之上的区域的基底和在导电材料区域上的电介质第一侧壁间隔物来制造。第二侧壁间隔件形成在从相对于第一侧壁间隔件选择性地移除的材料延伸到基板的第一侧壁间隔物的上方。形成接触第二侧壁间隔物并与衬底隔开的导电区域。第二侧壁间隔件可选择性地移除以在基板和导电区域之间形成开口。开口填充有导电材料以将导电材料电耦合到基底。

9. 发明授权

US06271577B1 Transistor and method 有权
标题翻译：晶体管和方法
公开(公告)号：US06271577B1
公开(公告)日：2001-08-07
申请号：US09212136
申请日：1998-12-15
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L27082
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/1004 , H01L29/7322
摘要： A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.
摘要翻译：一种制造半导体器件和器件的方法。该器件通过提供具有导电材料之上的区域的基底和在导电材料区域上的电介质第一侧壁间隔物来制造。第二侧壁间隔件形成在从相对于第一侧壁间隔件选择性地移除的材料延伸到基板的第一侧壁间隔物的上方。形成接触第二侧壁间隔物并与衬底隔开的导电区域。第二侧壁间隔件可选择性地移除以在基板和导电区域之间形成开口。开口填充有导电材料以将导电材料电耦合到基底。

10. 发明授权

US6130156A Variable doping of metal plugs for enhanced reliability 有权
标题翻译：金属插头的可变掺杂可提高可靠性
公开(公告)号：US6130156A
公开(公告)日：2000-10-10
申请号：US281538
申请日：1999-03-30
申请人： Robert H. Havemann , Girish A. Dixit , Stephen W. Russell
发明人： Robert H. Havemann , Girish A. Dixit , Stephen W. Russell
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76876 , H01L21/76877 , H01L21/76886 , H01L2221/1089 , H01L23/53219 , H01L23/53233 , H01L2924/0002
摘要： A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via. The first layer of electrically conductive interconnect is preferably aluminum, the first layer of electrically conductive metal is preferably a metal containing from about one percent by weight to about one hundred percent copper and the rest essentially aluminum and the second layer of electrically conductive metal is preferably copper doped aluminum having a lower copper content than the first electrically conductive layer.
摘要翻译：一种制造互连的方法，其中最初提供第一层导电互连（3）。形成通孔（7），其通过延伸到第一互连层的壁限定。在导电互连和导电金属（11）的第一层之间形成一层钛（9）。第一层导电金属形成在通孔的壁上，具有相对于特定蚀刻物质的预定蚀刻速率，并且第二层导电金属（13）形成在具有蚀刻的第一导电金属层上相对于比第一层大的特定蚀刻物质的速率，并且优选地延伸到通孔中。导电互连的第一层优选为铝，第一层导电金属优选为含有约1％至约100％铜的金属，其余基本上为铝，而第二层导电金属优选为铜掺杂的铝的铜含量低于第一导电层。

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