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1. 发明授权

US07506081B2 System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories 失效
标题翻译：从低带宽存储器维持数据管道的高带宽需求的系统和方法
公开(公告)号：US07506081B2
公开(公告)日：2009-03-17
申请号：US10850219
申请日：2004-05-20
申请人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G06F3/00
CPC分类号： G11C7/1066 , G11C7/1039 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.
摘要翻译：网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。

2. 发明授权

US06532185B2 Distribution of bank accesses in a multiple bank DRAM used as a data buffer 有权
公开(公告)号：US06532185B2
公开(公告)日：2003-03-11
申请号：US09792605
申请日：2001-02-23
申请人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G11C800
CPC分类号： H04L49/901 , G06F12/0607 , H04L49/90 , H04L49/9031
摘要： Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

3. 发明授权

US08219745B2 Memory controller to utilize DRAM write buffers 有权
标题翻译：存储器控制器利用DRAM写入缓冲器
公开(公告)号：US08219745B2
公开(公告)日：2012-07-10
申请号：US11002556
申请日：2004-12-02
申请人： Mark David Bellows , Kent Harold Haselhorst , Ryan Abel Heakendorf , Paul Allen Ganfield , Tolga Ozguner
发明人： Mark David Bellows , Kent Harold Haselhorst , Ryan Abel Heakendorf , Paul Allen Ganfield , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G06F13/1673
摘要： A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.
摘要翻译：提供了一种方法，装置和计算机程序来解释存储在动态随机存取存储器（DRAM）写入缓冲器中的数据。跟踪存储在DRAM写入缓冲器中的数据是困难的。为了缓解困难，采用缓存行列表。缓存行列表被保存在存储器控制器中，该存储器控制器被数据移动更新。该列表允许轻松维护数据而不失一致性。

4. 发明申请

US20090119442A1 Managing Write-to-Read Turnarounds in an Early Read After Write Memory System 有权
标题翻译：在写入内存系统后的早期读取中管理写入阅读的周转
公开(公告)号：US20090119442A1
公开(公告)日：2009-05-07
申请号：US12349240
申请日：2009-01-06
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
IPC分类号： G06F12/06
CPC分类号： G06F13/161 , G06F13/1647
摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译：介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号一个奇怪的DRAM银行。

5. 发明授权

US07272692B2 Arbitration scheme for memory command selectors 有权
标题翻译：存储器命令选择器的仲裁方案
公开(公告)号：US07272692B2
公开(公告)日：2007-09-18
申请号：US10988311
申请日：2004-11-12
申请人： Melissa Ann Barnum , Kent Harold Haselhorst , Lonny Lambrecht
发明人： Melissa Ann Barnum , Kent Harold Haselhorst , Lonny Lambrecht
IPC分类号： G06F12/00
CPC分类号： G06F13/1626
摘要： An arbitration structure, a method, and a computer program are provided for an arbitration scheme that can handle a plurality of memory commands in an operating system. Typically, in a memory system there are three types of memory commands: periodic, read, and write. An arbitration scheme determines the order of priority in which these commands are executed. This arbitration scheme is flexible because it contains a read/write priority module, which can be programmed to execute any order of priority combination of read and write commands. This enables an arbitration scheme for any memory system to be easily programmed for maximum efficiency.
摘要翻译：提供了一种可以处理操作系统中的多个存储器命令的仲裁方案的仲裁结构，方法和计算机程序。通常，在存储器系统中存在三种类型的存储器命令：周期性，读取和写入。仲裁方案确定执行这些命令的优先级顺序。该仲裁方案是灵活的，因为它包含一个读/写优先级模块，该模块可被编程为执行读和写命令的任意优先级组合顺序。这使得可以容易地编程任何存储器系统的仲裁方案以获得最大的效率。

6. 发明授权

US06188627B1 Method and system for improving DRAM subsystem performance using burst refresh control 失效
标题翻译：使用突发刷新控制来提高DRAM子系统性能的方法和系统
公开(公告)号：US06188627B1
公开(公告)日：2001-02-13
申请号：US09374200
申请日：1999-08-13
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018
摘要： A method and system for improving DRAM performance using burst refresh control reduces the overhead associated with refreshing DRAM in a computer system, making the memory more available to the devices that access it. Limiting the burst cycle to less than the entire DRAM array provides a lower latency than existing full DRAM burst techniques.
摘要翻译：使用突发刷新控制来提高DRAM性能的方法和系统减少了与计算机系统中的刷新DRAM相关联的开销，使得存储器对于访问它的设备更为可用。将突发周期限制为小于整个DRAM阵列提供比现有的全DRAM突发技术更低的延迟。

7. 发明授权

US07321950B2 Method and apparatus for managing write-to-read turnarounds in an early read after write memory system 有权
标题翻译：用于在写入存储器系统之后的早期读取中管理写入读取周转的方法和装置
公开(公告)号：US07321950B2
公开(公告)日：2008-01-22
申请号：US11050021
申请日：2005-02-03
申请人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
发明人： Mark David Bellows , Paul Allen Ganfield , Kent Harold Haselhorst , Ryan Abel Heckendorf , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1647
摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
摘要翻译：提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信号一个奇怪的DRAM银行。

8. 发明授权

US06628662B1 Method and system for multilevel arbitration in a non-blocking crossbar switch 有权
标题翻译：非阻塞交叉开关中多级仲裁的方法和系统
公开(公告)号：US06628662B1
公开(公告)日：2003-09-30
申请号：US09450792
申请日：1999-11-29
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： H04L12413
CPC分类号： H04L49/254 , H04L49/101 , H04L49/201 , H04L49/205
摘要： A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred. The deferred data transfer operations are prioritized within the multiple arbitration controllers, such that for a subsequent selection of the deferred data transfer operations, the switch is enabled for the deferred data transfer operations.
摘要翻译：一种用于仲裁在交换机通过电子隔离总线连接的设备之间的数据传输的方法和系统。根据本发明的方法和系统，多个仲裁控制器被插在设备之间和设备连接的交换机之间，其中多个仲裁控制器中的每一个有效地选择数据传输操作并检测所选择的数据传输操作。对于未检测到碰撞的任何所选数据传输操作，该开关被使能。只有在检测到碰撞之间的所选数据传输操作中的一个时，该开关也被使能。任何未启用交换机的选定数据传输操作都会被延迟。延迟数据传输操作在多个仲裁控制器内被优先排列，使得对于延迟数据传输操作的后续选择，该交换机被启用用于延迟数据传输操作。

9. 发明授权

US06557069B1 Processor-memory bus architecture for supporting multiple processors 失效
标题翻译：用于支持多个处理器的处理器 - 内存总线架构
公开(公告)号：US06557069B1
公开(公告)日：2003-04-29
申请号：US09439189
申请日：1999-11-12
申请人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella , George Wayne Nation
发明人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella , George Wayne Nation
IPC分类号： G06F1300
CPC分类号： G06F15/16
摘要： An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately. The data portion of the network comprises a set of bi-directional links from the processors to a local data switch unit (DSW). The local DSW is further linked directly to memory via bi-directional links. No address is transmitted with the data; rather, a tag is transmitted which identifies the original command.
摘要翻译：内部处理器/存储器总线包含用于发送地址和命令的地址部分，在处理器和本地中继器（ARP）之间以及ARP和中央中继器（ASW）之间具有一系列分层单向链路。命令从请求设备传播到其本地ARP，传送到ASW。从ASW，该命令通过传输到所有ARP或直接连接的内存，从ARP广播到总线上的所有设备。优选地，ASW全局仲裁地址总线，并且所有命令以预定义的时钟周期通过总线传播。优选地，总线上的每个设备独立地通过直接运行到全局收集器的单独响应链路来发送响应，该收集器收集所有响应并将单个系统范围响应广播到设备。在优选实施例中，地址/命令和数据在具有不同拓扑的基本上独立的路径上传输，并且在不同的时间被分开仲裁。网络的数据部分包括从处理器到本地数据交换单元（DSW）的一组双向链路。本地DSW通过双向链路进一步直接连接到存储器。没有地址与数据一起传输; 而是发送标识原始命令的标签。

10. 发明授权

US5748919A Shared bus non-sequential data ordering method and apparatus 失效
公开(公告)号：US5748919A
公开(公告)日：1998-05-05
申请号：US677775
申请日：1996-07-10
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F13/42 , G06F13/40 , G06F12/00 , G06F13/00
CPC分类号： G06F13/4018
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

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