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1. 发明授权

US07707463B2 Implementing directory organization to selectively optimize performance or reliability 有权
标题翻译：实施目录组织以选择性地优化性能或可靠性
公开(公告)号：US07707463B2
公开(公告)日：2010-04-27
申请号：US11290894
申请日：2005-11-30
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F11/00
CPC分类号： G06F11/1064 , G06F12/082
摘要： A method, and apparatus are provided for implementing a directory organization to selectively optimize performance or reliability in a computer system. A directory includes a user selected operational modes including a performance mode and a reliability mode. In the reliability mode, more directory bits are used for error correction and detection. In the performance mode, reclaimed directory bits not used for error correction and detection are used for more associativity.
摘要翻译：提供了一种用于实现目录组织以选择性地优化计算机系统中的性能或可靠性的方法和装置。目录包括用户选择的操作模式，包括演奏模式和可靠性模式。在可靠性模式下，更多的目录位用于纠错和检测。在性能模式下，不用于纠错和检测的回收目录位用于更多的关联性。

2. 发明授权

US07703063B2 Implementing memory read data eye stretcher 失效
标题翻译：实现内存读数据眼担架
公开(公告)号：US07703063B2
公开(公告)日：2010-04-20
申请号：US11840394
申请日：2007-08-17
申请人： William Paul Hovis , Paul W. Rudrud
发明人： William Paul Hovis , Paul W. Rudrud
IPC分类号： G06F17/50
CPC分类号： G11C11/4076 , G11C7/1042 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C11/4093
摘要： A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.
摘要翻译：实现高速的方法和数据接收装置，例如双倍数据速率（DDR），存储器读数据眼担架。执行改变参考电平以增加数据眼睛的大小。使用先前数据状态的知识来调整被锁存的当前数据的参考电平，使得数据眼睛被最大化。

3. 发明授权

US07603528B2 Memory device verification of multiple write operations 失效
标题翻译：多个写入操作的内存设备验证
公开(公告)号：US07603528B2
公开(公告)日：2009-10-13
申请号：US10961745
申请日：2004-10-08
申请人： William Hugh Cochran , William Paul Hovis , Paul Rudrud
发明人： William Hugh Cochran , William Paul Hovis , Paul Rudrud
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F12/0804 , G06F12/084
摘要： Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.
摘要翻译：利用验证操作来有效地验证多个关联的写入操作。可以在发出数据到存储器存储设备的多个写入操作的发出之后启动验证操作，并且可以被配置为仅通过多个写入验证写入存储器存储设备的数据的子集操作。结果，在每次写入操作之后不需要执行验证操作，因此可以显着减少验证操作的数量，从而可以大大减少由此消耗的处理和通信带宽。

4. 发明授权

US07526692B2 Diagnostic interface architecture for memory device 有权
标题翻译：内存设备的诊断接口架构
公开(公告)号：US07526692B2
公开(公告)日：2009-04-28
申请号：US10955735
申请日：2004-09-30
申请人： John Michael Borkenhagen , William Paul Hovis , James Anthony Marcella , Paul Rudrud
发明人： John Michael Borkenhagen , William Paul Hovis , James Anthony Marcella , Paul Rudrud
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/5602
摘要： A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.
摘要翻译：用于存储器设备的诊断接口架构在一个方面支持通常与从存储器件读取数据和/或将数据写入存储器件一起使用的一个或多个动态可重新配置的功能互连。动态可重构功能互连能够被配置为以功能或诊断模式操作，由此在诊断模式中，这种互连可以用于传送诊断信息以支持一个或多个诊断操作。诊断接口架构还可以支持给定存储器设备中的多个诊断接口，其中至少一个这样的诊断接口能够响应于另一诊断接口中的故障被选择性地启用。

5. 发明授权

US07517764B2 Bulk FinFET device 有权
标题翻译：散装FinFET器件
公开(公告)号：US07517764B2
公开(公告)日：2009-04-14
申请号：US11427486
申请日：2006-06-29
申请人： Roger Allen Booth, Jr. , William Paul Hovis , Jack Allan Mandelman
发明人： Roger Allen Booth, Jr. , William Paul Hovis , Jack Allan Mandelman
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。该结构包括在finFET的硅体和衬底之间的体接触。

6. 发明申请

US20090046812A1 Method and Data Receiver Apparatus for Implementing Memory Read Data Eye Stretcher 失效
标题翻译：用于实现存储器读取数据的担架的方法和数据接收装置
公开(公告)号：US20090046812A1
公开(公告)日：2009-02-19
申请号：US11840394
申请日：2007-08-17
申请人： William Paul Hovis , Paul W. Rudrud
发明人： William Paul Hovis , Paul W. Rudrud
IPC分类号： H04L25/06
CPC分类号： G11C11/4076 , G11C7/1042 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C11/4093
摘要： A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.
摘要翻译：实现高速的方法和数据接收装置，例如双倍数据速率（DDR），存储器读数据眼担架。执行改变参考电平以增加数据眼睛的大小。使用先前数据状态的知识来调整被锁存的当前数据的参考电平，使得数据眼睛被最大化。

7. 发明申请

US20080233699A1 BULK FinFET DEVICE 有权
标题翻译：大容量FinFET器件
公开(公告)号：US20080233699A1
公开(公告)日：2008-09-25
申请号：US12133440
申请日：2008-06-05
申请人： Roger Allen Booth , William Paul Hovis , Jack Allan Mandelman
发明人： Roger Allen Booth , William Paul Hovis , Jack Allan Mandelman
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。该结构包括在finFET的硅体和衬底之间的体接触。

8. 发明授权

US07317217B2 Semiconductor scheme for reduced circuit area in a simplified process 失效
标题翻译：减少电路面积的半导体方案
公开(公告)号：US07317217B2
公开(公告)日：2008-01-08
申请号：US10944626
申请日：2004-09-17
申请人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
发明人： Todd Alan Christensen , Richard Lee Donze , William Paul Hovis , Terrance Wayne Kueper , John Edward Sheets, II
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L29/458 , H01L29/785
摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
摘要翻译：公开了一种使用简化过程的改进的半导体互连方案的装置和方法。在该装置的实施例中，在硅区域上形成多晶硅形状。产生具有桥接顶点的多晶硅形状。当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。

9. 发明授权

US07225375B2 Method and apparatus for detecting array degradation and logic degradation 有权
标题翻译：用于检测阵列退化和逻辑劣化的方法和装置
公开(公告)号：US07225375B2
公开(公告)日：2007-05-29
申请号：US10815248
申请日：2004-03-31
申请人： William Hugh Cochran , William Paul Hovis
发明人： William Hugh Cochran , William Paul Hovis
IPC分类号： G01R31/28
CPC分类号： G11C29/50012 , G01R31/318516 , G11C29/14 , G11C29/50 , G11C2029/5004
摘要： A method and apparatus are provided for detecting degradation, such as, array degradation and logic degradation, in integrated circuits (ICs) including application specific integrated circuits (ASICs). A monitor built-in self-test (MBIST) engine coupled to at least one monitor element that is defined by predefined circuit elements in the integrated circuit. The MBIST engine is used for controlling operation of at least one monitor element for communicating with monitor bits to identify degradation of signal, timing and voltage margins.
摘要翻译：提供了一种用于在包括专用集成电路（ASIC））的集成电路（IC）中检测诸如阵列劣化和逻辑劣化的劣化的方法和装置。耦合到由集成电路中的预定义电路元件定义的至少一个监视器元件的监视器内置自检（MBIST）引擎。 MBIST引擎用于控制至少一个监视元件的操作，用于与监视位进行通信，以识别信号的劣化，定时和电压裕度。

10. 发明授权

US07129769B2 Method and apparatus for protecting eFuse information 失效
标题翻译：保护eFuse信息的方法和装置
公开(公告)号：US07129769B2
公开(公告)日：2006-10-31
申请号：US11060355
申请日：2005-02-17
申请人： Robert Christopher Dixon , William Paul Hovis , Kirk Edward Morrow
发明人： Robert Christopher Dixon , William Paul Hovis , Kirk Edward Morrow
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , G11C16/22
摘要： A method and apparatus are provided for protecting electronic fuse (eFuse) information. A current balancing circuit is provided that maintains a constant current demand on the eFuse voltage supply that is sufficient to blow an eFuse. Normally the constant current is applied to a semiconductor core. When an eFuse is being blown, the constant current is diverted away from the core to the eFuse and as the eFuse blows, the constant current is again dumped to the semiconductor core. Thus, a change in current due to the transient of the eFuse being blown is not detectable and the information that an eFuse has been blown is kept secure.
摘要翻译：提供了一种用于保护电子熔丝（eFuse）信息的方法和装置。提供了一种电流平衡电路，其对足以吹入eFuse的eFuse电压源保持恒定的电流需求。通常，将恒定电流施加到半导体芯。当eFuse被吹制时，恒定电流从核心转移到eFuse，并且当eFuse烧断时，恒定电流再次被转移到半导体核心。因此，由于eFuse的瞬态被吹过而导致的电流变化是不可检测的，并且eFuse已经被熔断的信息保持安全。

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