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1. 发明授权

US06188627B1 Method and system for improving DRAM subsystem performance using burst refresh control 失效
标题翻译：使用突发刷新控制来提高DRAM子系统性能的方法和系统
公开(公告)号：US06188627B1
公开(公告)日：2001-02-13
申请号：US09374200
申请日：1999-08-13
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , William Paul Hovis , James Anthony Marcella
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C7/1018
摘要： A method and system for improving DRAM performance using burst refresh control reduces the overhead associated with refreshing DRAM in a computer system, making the memory more available to the devices that access it. Limiting the burst cycle to less than the entire DRAM array provides a lower latency than existing full DRAM burst techniques.
摘要翻译：使用突发刷新控制来提高DRAM性能的方法和系统减少了与计算机系统中的刷新DRAM相关联的开销，使得存储器对于访问它的设备更为可用。将突发周期限制为小于整个DRAM阵列提供比现有的全DRAM突发技术更低的延迟。

2. 发明授权

US06513091B1 Data routing using status-response signals 失效
标题翻译：使用状态响应信号的数据路由
公开(公告)号：US06513091B1
公开(公告)日：2003-01-28
申请号：US09439586
申请日：1999-11-12
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： G06F1314
CPC分类号： G06F13/14
摘要： A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.
摘要翻译：一种用于在总线设备之间路由数据的方法和设备，其中每个总线设备经由点到点总线连接连接到集中式交换机。多个点到点总线连接共同形成系统总线。在系统总线上发出命令之后，每个总线设备通过向响应组合逻辑模块发送地址状态响应来响应发出的命令。响应组合逻辑模块识别哪个总线设备对所发出的命令进行肯定确认响应，然后将响应于肯定确认的总线设备的设备标识符转发给交换机。交换机使用通过响应组合逻辑返回的设备标识符来路由与发出的命令相关联的数据传输。

3. 发明授权

US06505306B1 Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization 失效
标题翻译：冗余位转向机制，在冗余设备初始化期间具有提取操作的延迟切换
公开(公告)号：US06505306B1
公开(公告)日：2003-01-07
申请号：US09396973
申请日：1999-09-15
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： H02H305
CPC分类号： G11C29/76
摘要： An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.
摘要翻译：装置，程序产品和方法通过将非初始化获取操作从故障存储器设备切换到冗余存储器设备来初始化冗余存储器件，直到冗余存储器件的初始化完成为止。因此，在初始化期间，非初始化提取操作被定向到故障存储器设备，而非初始化存储操作被引导到冗余设备。

4. 发明授权

US06628662B1 Method and system for multilevel arbitration in a non-blocking crossbar switch 有权
标题翻译：非阻塞交叉开关中多级仲裁的方法和系统
公开(公告)号：US06628662B1
公开(公告)日：2003-09-30
申请号：US09450792
申请日：1999-11-29
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： H04L12413
CPC分类号： H04L49/254 , H04L49/101 , H04L49/201 , H04L49/205
摘要： A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred. The deferred data transfer operations are prioritized within the multiple arbitration controllers, such that for a subsequent selection of the deferred data transfer operations, the switch is enabled for the deferred data transfer operations.
摘要翻译：一种用于仲裁在交换机通过电子隔离总线连接的设备之间的数据传输的方法和系统。根据本发明的方法和系统，多个仲裁控制器被插在设备之间和设备连接的交换机之间，其中多个仲裁控制器中的每一个有效地选择数据传输操作并检测所选择的数据传输操作。对于未检测到碰撞的任何所选数据传输操作，该开关被使能。只有在检测到碰撞之间的所选数据传输操作中的一个时，该开关也被使能。任何未启用交换机的选定数据传输操作都会被延迟。延迟数据传输操作在多个仲裁控制器内被优先排列，使得对于延迟数据传输操作的后续选择，该交换机被启用用于延迟数据传输操作。

5. 发明授权

US5748919A Shared bus non-sequential data ordering method and apparatus 失效
公开(公告)号：US5748919A
公开(公告)日：1998-05-05
申请号：US677775
申请日：1996-07-10
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F13/42 , G06F13/40 , G06F12/00 , G06F13/00
CPC分类号： G06F13/4018
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

6. 发明授权

US06895482B1 Reordering and flushing commands in a computer memory subsystem 失效
标题翻译：在计算机内存子系统中重新排序和刷新命令
公开(公告)号：US06895482B1
公开(公告)日：2005-05-17
申请号：US09394011
申请日：1999-09-10
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Kent Harold Haselhorst , James Anthony Marcella
IPC分类号： G06F9/38 , G06F12/00
CPC分类号： G06F9/3824 , G06F3/0659 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3859
摘要： An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution. Memory commands of that type are selected for execution each subsequent cycle until a valid memory command of that type is no longer available, or until a predetermined number has been executed, or until a memory command of another type has higher priority. If an address dependency exists between memory commands of different types, then memory commands of the same type of the oldest memory command is executed to avoid deadlock.
摘要翻译：改进的计算机存储器子系统确定执行最有效的存储器命令。确定每个传入存储器命令到存储器控制器的物理位置和任何地址依赖性，并且该信息伴随着用于分类为命令类型的命令。对于每种类型的存储器命令，存在命令FIFO和相关联的逻辑，其中存储器命令的可编程数目被选择用于当前正在执行的存储器命令以及先前选择用于执行的存储器命令之间的比较。选择具有最少存储周期性能损失的存储器命令用于执行，除非该存储器命令具有地址依赖性。如果该类型的多个存储器命令具有最小的内存周期性能损失，则选择最旧的内存命令执行。选择该类型的存储器命令用于每个后续周期执行，直到该类型的有效存储器命令不再可用，或者直到预定号码已被执行，或者直到另一类型的存储器命令具有较高优先级为止。如果不同类型的存储器命令之间存在地址依赖关系，则执行相同类型的最旧存储器命令的存储器命令以避免死锁。

7. 发明授权

US06523080B1 Shared bus non-sequential data ordering method and apparatus 失效
标题翻译：共享总线非顺序数据排序方法和装置
公开(公告)号：US06523080B1
公开(公告)日：2003-02-18
申请号：US09014090
申请日：1998-01-27
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F1342
CPC分类号： G06F13/385
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
摘要翻译：提供共享总线非顺序数据排序方法和装置。识别最大总线宽度值和最小传输值。响应于所识别的最大总线宽度值和最小传输值来识别最小数量的子传送。具有用于接收和/或发送数据的最大数量的码片的总线单元在多个子传送期间以预定义的顺序接收数据。在每个数据子传送期间，相应的预定义字被传送到总线单元的每个芯片。

8. 发明授权

US06557069B1 Processor-memory bus architecture for supporting multiple processors 失效
标题翻译：用于支持多个处理器的处理器 - 内存总线架构
公开(公告)号：US06557069B1
公开(公告)日：2003-04-29
申请号：US09439189
申请日：1999-11-12
申请人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella , George Wayne Nation
发明人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella , George Wayne Nation
IPC分类号： G06F1300
CPC分类号： G06F15/16
摘要： An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately. The data portion of the network comprises a set of bi-directional links from the processors to a local data switch unit (DSW). The local DSW is further linked directly to memory via bi-directional links. No address is transmitted with the data; rather, a tag is transmitted which identifies the original command.
摘要翻译：内部处理器/存储器总线包含用于发送地址和命令的地址部分，在处理器和本地中继器（ARP）之间以及ARP和中央中继器（ASW）之间具有一系列分层单向链路。命令从请求设备传播到其本地ARP，传送到ASW。从ASW，该命令通过传输到所有ARP或直接连接的内存，从ARP广播到总线上的所有设备。优选地，ASW全局仲裁地址总线，并且所有命令以预定义的时钟周期通过总线传播。优选地，总线上的每个设备独立地通过直接运行到全局收集器的单独响应链路来发送响应，该收集器收集所有响应并将单个系统范围响应广播到设备。在优选实施例中，地址/命令和数据在具有不同拓扑的基本上独立的路径上传输，并且在不同的时间被分开仲裁。网络的数据部分包括从处理器到本地数据交换单元（DSW）的一组双向链路。本地DSW通过双向链路进一步直接连接到存储器。没有地址与数据一起传输; 而是发送标识原始命令的标签。

9. 再颁专利

USRE44342E1 Bus architecture employing varying width uni-directional command bus 有权
公开(公告)号：USRE44342E1
公开(公告)日：2013-07-02
申请号：US11203652
申请日：2005-08-15
申请人： Robert Allen Drehmel , Kent Harold Haselhorst , Russel Dean Hoover , James Anthony Marcella
发明人： Robert Allen Drehmel , Kent Harold Haselhorst , Russel Dean Hoover , James Anthony Marcella
IPC分类号： G06F12/00 , G06F13/00
摘要： A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again. Preferably, the central repeater globally arbitrates the bus, and once the bus is granted, the command propagates along each link at pre-defined clock cycles from bus grant. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately.

10. 发明授权

US06526469B1 Bus architecture employing varying width uni-directional command bus 有权
标题翻译：总线架构采用不同宽度的单向命令总线
公开(公告)号：US06526469B1
公开(公告)日：2003-02-25
申请号：US09439068
申请日：1999-11-12
申请人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella
发明人： Robert Allen Drehmel , Kent Harold Haselhorst , Russell Dean Hoover , James Anthony Marcella
IPC分类号： G06F1300
CPC分类号： G06F13/4013
摘要： A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again. Preferably, the central repeater globally arbitrates the bus, and once the bus is granted, the command propagates along each link at pre-defined clock cycles from bus grant. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately.
摘要翻译：处理器存储器总线包括用于发送地址和命令的命令部分，具有用于向中央中继器单元发送命令的单向输入部分和用于从中继器广播命令的单向广播部分。输入部分包括从不同设备运行的多个链路，其中每个链路小于广播总线部分的整个宽度。在多个总线周期中通过输入部分发送命令，并且在单个总线周期中通过广播部分进行广播。由于多个输入链路连接到中央命令中继器，因此尽管在输入部分上传送单个命令需要多个总线周期，仍然可以使广播总线保持充分。优选地，链路从处理器到本地中继器分层布置，从本地中继器到中央中继器，并且再次返回。优选地，中央中继器全局地仲裁总线，并且一旦总线被授权，该命令沿着每个链路以预定义的时钟周期从总线授权传播。在优选实施例中，地址/命令和数据在具有不同拓扑的基本上独立的路径上传输，并且在不同的时间被分开仲裁。

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