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1. 发明授权

US07535912B2 Bi-lateral bandwidth negotiation upon detection of a short-term traffic pattern change 失效
标题翻译：检测到短期流量模式变化时的双向带宽协商
公开(公告)号：US07535912B2
公开(公告)日：2009-05-19
申请号：US10963647
申请日：2004-10-14
申请人： Peter Irma August Barri , Bart Joseph Gerard Pauwels , Geert René Taildemand
发明人： Peter Irma August Barri , Bart Joseph Gerard Pauwels , Geert René Taildemand
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L47/70 , H04L47/765 , H04L47/801 , H04L47/825 , H04L47/826
摘要： The present invention relates to a switching unit with a low-latency flow control. Queuing parameters of ingress queues, wherein the incoming traffic is backlogged, are measured to detect a short term traffic increase. An additional bandwidth is then negotiated to accommodate this unexpected additional amount of traffic, provided that the corresponding input and output termination modules still dispose of available bandwidth, and disregarding temporarily fairness. This additional bandwidth allows this unexpected additional amount of traffic to be drained from the ingress queue as soon as possible, without waiting for the next system bandwidth fair re-distribution, thereby improving the traffic latency through the switching unit.
摘要翻译：本发明涉及具有低等待时间流量控制的切换单元。测量进入流量被积压的入口队列的排队参数，以检测短期流量增加。然后协商额外的带宽以适应这种意想不到的额外的流量，只要相应的输入和输出终端模块仍然处理可用带宽，并忽略暂时的公平性。这种额外的带宽允许尽可能快地从入口队列中排除这种意想不到的额外的流量，而不用等待下一个系统带宽公平的重新分配，从而通过交换单元改善流量等待时间。

2. 发明授权

US07522624B2 Scalable and QoS aware flow control 有权
标题翻译：可扩展和QoS感知流量控制
公开(公告)号：US07522624B2
公开(公告)日：2009-04-21
申请号：US10965844
申请日：2004-10-18
申请人： Peter Irma August Barri , Bart Joseph Gerard Pauwels , Geert René Taildemand
发明人： Peter Irma August Barri , Bart Joseph Gerard Pauwels , Geert René Taildemand
IPC分类号： H04L12/28
CPC分类号： H04L47/10 , H04L47/50 , H04L47/522 , H04L47/6215 , H04L47/623 , H04L47/6255 , H04L49/101 , H04L49/254
摘要： The present invention relates to a switching unit with a scalable and QoS aware flow control. The actual schedule rate of an egress queue, wherein the outgoing traffic belonging to a particular class of service is backlogged, is measured and compared to its expected schedule rate. If the egress queue is scheduled below expectation, then the bandwidth of every virtual ingress-to-egress pipe connecting an ingress queue, wherein the incoming traffic belonging to the same class of service is backlogged before transmission through the switch core fabric, to that egress queue is increased, thereby feeding that egress queue with more data units.
摘要翻译：本发明涉及具有可扩展和QoS感知流量控制的切换单元。测量排出队列的实际调度速率，其中属于特定服务等级的输出业务被重新填充，并与其预期调度速率进行比较。如果出口队列调度低于期望值，则连接入口队列的每个虚拟入口到出口管道的带宽，其中属于相同等级的服务的入站流量在通过交换机核心架构传输之前被积压到该出口队列增加，从而为更多的数据单元提供出口队列。

3. 发明授权

US07506081B2 System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories 失效
标题翻译：从低带宽存储器维持数据管道的高带宽需求的系统和方法
公开(公告)号：US07506081B2
公开(公告)日：2009-03-17
申请号：US10850219
申请日：2004-05-20
申请人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Jean Louis Calvignac , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G06F3/00
CPC分类号： G11C7/1066 , G11C7/1039 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.
摘要翻译：网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。

4. 发明授权

US06469982B1 Method to share available bandwidth, a processor realizing such a method, and a scheduler, an intelligent buffer and a telecommunication system including such a processor 有权
标题翻译：共享可用带宽的方法，实现这种方法的处理器，以及包括这种处理器的调度器，智能缓冲器和电信系统
公开(公告)号：US06469982B1
公开(公告)日：2002-10-22
申请号：US09363039
申请日：1999-07-29
申请人： Michel André Robert Henrion , Olivier Bonaventure , Peter Irma August Barri , Emmanuel Desmet , Johan Gabriël August Verkinderen
发明人： Michel André Robert Henrion , Olivier Bonaventure , Peter Irma August Barri , Emmanuel Desmet , Johan Gabriël August Verkinderen
IPC分类号： H04J324
CPC分类号： H04L12/5602 , H04L2012/5632 , H04L2012/5651 , H04Q11/0478
摘要： The method shares available bandwidth on a common link in a communication network among a plurality of data flows which are transmitted via the common link. The method is used by a processor and includes sharing reserved bandwidth included in the available bandwidth among the plurality of data flows, and sharing unreserved bandwidth among the plurality of data flows according to a respective unreserved data packet share which is associated to each one of the plurality of data flows. The unreserved bandwidth is included in the available bandwidth in excess of the reserved bandwidth. The sharing of the unreserved bandwidth includes associating to one of the plurality of data flows a respective adaptable administrative weight and determining the respective unreserved data packet share which is associated to the one data flow as a function of its respective adaptable administrative weight.
摘要翻译：该方法在通过公共链路发送的多个数据流中的通信网络中的公共链路上共享可用带宽。所述方法由处理器使用，并且包括在所述多个数据流之间共享包括在所述可用带宽中的保留带宽，以及根据与所述多个数据流中的每一个相关联的相应未保留的数据分组共享在所述多个数据流之间共享未保留的带宽多个数据流。未预留的带宽被包含在可用带宽中超过预留带宽。未预留带宽的共享包括将相应的可适应管理权重中的一个数据流相关联，并且根据其相应的适应管理权重确定与一个数据流相关联的相应的未预留数据分组共享。

5. 发明授权

US08045549B2 Method and apparatus for packet reordering in a network processor 有权
标题翻译：网络处理器中数据包重新排序的方法和装置
公开(公告)号：US08045549B2
公开(公告)日：2011-10-25
申请号：US10389929
申请日：2003-03-18
申请人： Peter Irma August Barri , Miroslav Vrana , Robert Elliott Robotham
发明人： Peter Irma August Barri , Miroslav Vrana , Robert Elliott Robotham
IPC分类号： H04L12/28
CPC分类号： H04Q3/66 , H04L47/34 , H04Q2213/13106 , H04Q2213/13141 , H04Q2213/13166 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13296 , H04Q2213/13298 , H04Q2213/13348 , H04Q2213/13389
摘要： A method for packet reordering in a network processor, including the steps of processing packets, dividing the processed packets into a plurality of tiers and reordering the tiers independently from each other and collecting eligible packets from the plurality of tiers in a collector for forwarding. The method further includes the step of during the processing, determining the nominal packet processing time of each packet. The processed packets are divided into the plurality of tiers depending on the nominal packet processing time.
摘要翻译：一种网络处理器中的分组重新排序的方法，包括处理分组的步骤，将处理的分组划分成多个层，并且彼此独立地重排序层，并收集来自收集器中的多个层的合格分组以进行转发。该方法还包括在处理期间确定每个分组的标称分组处理时间的步骤。处理的分组根据标称分组处理时间被划分成多个层。

6. 发明授权

US06532185B2 Distribution of bank accesses in a multiple bank DRAM used as a data buffer 有权
公开(公告)号：US06532185B2
公开(公告)日：2003-03-11
申请号：US09792605
申请日：2001-02-23
申请人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Jean Louis Calvignac , Peter Irma August Barri , Ivan Oscar Clemminck , Kent Harold Haselhorst , Marco C. Heddes , Joseph Franklin Logan , Bart Joseph Gerard Pauwels , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： G11C800
CPC分类号： H04L49/901 , G06F12/0607 , H04L49/90 , H04L49/9031
摘要： Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

7. 发明授权

US07173901B2 Flow and congestion control in a switching network 有权
标题翻译：交换网络中的流量和拥塞控制
公开(公告)号：US07173901B2
公开(公告)日：2007-02-06
申请号：US10152283
申请日：2002-05-22
申请人： Bart Joseph Gerard Pauwels , Peter Irma August Barri
发明人： Bart Joseph Gerard Pauwels , Peter Irma August Barri
IPC分类号： H04J1/16
CPC分类号： H04L47/12 , H04L47/10 , H04L49/10
摘要： System for obtaining an efficient and scaleable flow control in a large packet switched network including ingress termination boards (B1″) linked to egress termination boards (B4″) by means of virtual ingress to egress flow control links through a switch core.The flow control transmission link between a port of an ingress termination board and a port of an egress termination board comprises at least two virtual ingress to egress flow controlled traffic pipes (VIEP″a, VIEP″b), one pipe handling all the traffic between the two ports which is going towards communication channels for which no congestion is detected at the level of the egress termination board, the other pipe handling all the traffic going towards communication channels for which congestion is detected.
摘要翻译：用于在大分组交换网络中获得有效和可扩展的流量控制的系统，包括通过虚拟入口链接到出口终端板（B 4“）的入口终端板（B 1”），以通过交换机核心流出流量控制链路。入口终端板的端口和出口终端板的端口之间的流控制传输链路包括至少两个虚拟入口到出口流控流量管道（VIEP'a，VIEP“b），一个管道处理所有在出口终端板的级别上不发生拥塞的通信信道的两个端口之间的业务，另一个管理器处理到检测到拥塞的通信信道的所有业务。

8. 发明授权

US06657962B1 Method and system for managing congestion in a network 失效
标题翻译：管理网络拥塞的方法和系统
公开(公告)号：US06657962B1
公开(公告)日：2003-12-02
申请号：US09546651
申请日：2000-04-10
申请人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： H04L1256
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/12 , H04L47/30 , H04L47/32 , H04L49/103 , H04L49/3018 , H04L49/50 , H04L49/90
摘要： A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue. The second congestion adjustment module generates and stores transmit probabilities and performs per packet flow control actions. Finally, the system includes a scheduler for determining the order and timing of transmission of packets out the egress system and to another node or destination. A method and system in accordance with the present invention provides for a unified method and system for logical connection of congestion with the appropriate flow control responses. The method and system utilizes congestion indicators within the ingress system, egress system, and the switch fabric in conjunction with a coarse adjustment system and fine adjustment system within the ingress device and the egress device to intelligently manage the system.
摘要翻译：公开了一种用于最小化通信系统中的拥塞的系统。该系统包括用于提供数据的至少一个入口系统。入口系统包括第一空闲队列和第一流队列。该系统还包括用于从空闲队列和流队列接收拥塞指示的第一拥塞调整模块。第一拥塞调整模块生成终端存储发送概率并执行每个分组流控制动作。该系统还包括用于从入口系统接收数据并向入口系统提供拥塞指示的交换结构。该系统还包括用于从交换结构接收数据的至少一个出口系统。出口系统包括第二空闲队列和第二流队列。该系统还包括第二拥塞调整模块，用于从第二空闲队列和第二流队列接收拥塞指示。第二拥塞调整模块生成并存储发送概率，并执行每个分组流控制动作。最后，该系统包括一个调度器，用于确定出口系统和另一个节点或目的地的分组传输的顺序和定时。根据本发明的方法和系统提供了用于将拥塞与适当流控制响应逻辑连接的统一方法和系统。该方法和系统利用入口系统，出口系统和交换结构中的拥塞指示符与入口设备和出口设备内的粗调系统和精细调整系统结合，智能地管理系统。

9. 发明授权

US08675655B2 Method for distributing load over multiple shared resources in a communication network and network applying such a method 有权
标题翻译：在通信网络中应用这种方法的多个共享资源上的负载分配方法
公开(公告)号：US08675655B2
公开(公告)日：2014-03-18
申请号：US10265446
申请日：2002-10-07
申请人： Peter Irma August Barri , Bart Joseph Gerard Pauwels , Tom Edward Davis , Olivier Didier Duroyon , Chad William Kendall , Predrag Kostic , Robert Nesbitt , Robert Elliott Robotham
发明人： Peter Irma August Barri , Bart Joseph Gerard Pauwels , Tom Edward Davis , Olivier Didier Duroyon , Chad William Kendall , Predrag Kostic , Robert Nesbitt , Robert Elliott Robotham
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/22 , H04L45/24 , H04L45/38 , H04L45/745 , H04L47/125
摘要： The invention relates to a telecommunication network having IP packet-supporting capabilities, which includes a load distribution processing function, either centralized or distributed, by means of which a load distribution function may be applied to sets of paths between network nodes or sets of links of network trunks. The load distribution processing function handles different load distribution functions. Each of the different load distribution functions is associated to a different network input unit involved in the load distribution for a set of paths between network nodes or a set of trunk links. The invention also relates to a method of load distribution in a telecommunication network as summarized above.
摘要翻译：本发明涉及具有IP分组支持能力的电信网络，其包括集中式或分布式的负载分配处理功能，通过该负载分配处理功能可以将负载分布功能应用于网络节点或链路集合之间的路径集合网络干线负载分配处理功能处理不同的负载分配功能。不同负载分配功能中的每一个都与网络节点或一组中继链路之间的一组路径的负载分配中涉及的不同网络输入单元相关联。本发明还涉及如上所述的电信网络中负载分配的方法。

10. 发明授权

US07106699B2 Method for sharing internal excess bandwidth between output and input termination modules of a switching network 有权
标题翻译：在交换网络的输出和输入终端模块之间共享内部超额带宽的方法
公开(公告)号：US07106699B2
公开(公告)日：2006-09-12
申请号：US09963517
申请日：2001-09-27
申请人： Peter Irma August Barri
发明人： Peter Irma August Barri
IPC分类号： H04J3/16 , H04L12/56
CPC分类号： H04L49/3081 , H04L12/5602 , H04L49/205 , H04L49/30 , H04L49/503 , H04L2012/5632 , H04L2012/5651 , H04L2012/5679 , H04Q11/0478
摘要： A method for sharing internal excess bandwidth between output and input termination modules of a switching network including a switch core fabric (FC) via which a plurality of input termination modules (ITM1 to ITMn) communicate with a plurality of output termination modules (OTM1 to OTMm) through at least a point-to-point transmission channels considered as corresponding each to a virtual ingress-to-egress pipe (VIEP). Sharing of internal excess bandwidth is obtained by successive steps including a minimum bandwidth request calculation step, each request being transmitted to an output termination module for obtaining a minimum bandwidth grant in return. The minimum bandwidth request and grant related to an input termination module linked by an ingress-to-egress pipe to an output termination module are both calculated for a determined number K of relative administrative weights corresponding each to a different quality of service, with a different request and a corresponding grant for every weight.
摘要翻译：一种用于在包括交换机核心结构（FC）的交换网络的输出和输入终端模块之间共享内部超额带宽的方法，多个输入终端模块（ITM 1至ITMn）经由多个输入终端模块（ITM 1至ITMn）与多个输出终端模块到OTMm），至少通过被认为对应于虚拟入口到出口管（VIEP）的点到点传输信道。通过包括最小带宽请求计算步骤的连续步骤获得内部超额带宽的共享，每个请求被发送到输出终端模块以获得最小带宽授权。对于由入口到出口管道链接到输出端接模块的输入终端模块的最小带宽请求和授权都是针对每个与不同服务质量相对应的确定数量K的相对管理权重而计算的，具有不同的请求和每个权重相应的授权。

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