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1. 发明授权

US07594058B2 Chipset supporting a peripheral component interconnection express (PCI-E) architecture 有权
标题翻译：芯片组支持外围组件互连快速（PCI-E）架构
公开(公告)号：US07594058B2
公开(公告)日：2009-09-22
申请号：US11267498
申请日：2005-11-07
申请人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
发明人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.
摘要翻译：使用PCI-E架构的本计算系统包括至少一个第一PCI-E端口，第一端口仲裁器，第一URD逻辑，微处理器，DARD逻辑和设备仲裁器。第一个端口仲裁器从第一个PCI-E端口接收数据。第一URD逻辑耦合到所述第一端口仲裁器。第一个URD逻辑包括板载范围表和PCI-E设备范围表，用于检测板上访问或对等访问的数据。微处理器接收并处理来自用于所述板载存取的第一URD逻辑的数据。 DARD逻辑从微处理器接收数据。 DARD逻辑解码数据的下游请求的设备范围。设备仲裁器耦合到DARD逻辑和第一个URD逻辑，用于将数据分配到第一个PCI-E端口之一。

2. 发明申请

US20070106826A1 Method and computer system using PCI-Express 有权
标题翻译：使用PCI-Express的方法和计算机系统
公开(公告)号：US20070106826A1
公开(公告)日：2007-05-10
申请号：US11267498
申请日：2005-11-07
申请人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
发明人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.
摘要翻译：使用PCI-E架构的本计算系统包括至少一个第一PCI-E端口，第一端口仲裁器，第一URD逻辑，微处理器，DARD逻辑和设备仲裁器。第一个端口仲裁器从第一个PCI-E端口接收数据。第一URD逻辑耦合到所述第一端口仲裁器。第一个URD逻辑包括板载范围表和PCI-E设备范围表，用于检测板上访问或对等访问的数据。微处理器接收并处理来自用于所述板载存取的第一URD逻辑的数据。 DARD逻辑从微处理器接收数据。 DARD逻辑解码数据的下游请求的设备范围。设备仲裁器耦合到DARD逻辑和第一个URD逻辑，用于将数据分配到第一个PCI-E端口之一。

3. 发明授权

US06571323B2 Memory-access management method and system for synchronous dynamic Random-Access memory or the like 有权
公开(公告)号：US06571323B2
公开(公告)日：2003-05-27
申请号：US10115780
申请日：2002-04-03
申请人： Jiin Lai , Chih-kuo Kao
发明人： Jiin Lai , Chih-kuo Kao
IPC分类号： G06F1200
CPC分类号： G06F12/0895 , G06F12/0215 , G06F12/123
摘要： A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.

4. 发明授权

US06490665B1 Memory-access management method and system for synchronous random-access memory or the like 有权
标题翻译：用于同步随机存取存储器的内存访问管理方法和系统等
公开(公告)号：US06490665B1
公开(公告)日：2002-12-03
申请号：US09350974
申请日：1999-07-09
申请人： Jiin Lai , Chih-kuo Kao , Chia-Hsin Chen
发明人： Jiin Lai , Chih-kuo Kao , Chia-Hsin Chen
IPC分类号： G06F1200
CPC分类号： G06F12/0895 , G06F12/123
摘要： A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit. A utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and moreover, a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.
摘要翻译：提供了一种与SDRAM（同步动态随机存取存储器）等一起使用的存储器访问管理方法和系统，用于通过跟踪存储器访问历史来增加对SDRAM的存储器访问的性能以前的访问操作。存储器页管理系统包括页表寄存器单元，其包括用于存储存储器单元的预定数量的最近访问的存储器位置的页表。此外，存储器页管理系统包括：比较单元，其能够响应于对存储器单元的每个访问请求，检查所请求的存储器位置是否是存储在页表寄存器单元中的页表中的任何一个的命中。利用率寄存器单元耦合到页表寄存器单元，用于监视存储在页表寄存器单元中的最近最少使用的记录; 此外，有效性检查单元耦合到页表寄存器单元，用于检查存储在页表寄存器单元中的页表中的地址数据是有效还是无效。

5. 发明授权

US07805567B2 Chipset and northbridge with raid access 有权
标题翻译：芯片组和北桥与突袭访问
公开(公告)号：US07805567B2
公开(公告)日：2010-09-28
申请号：US11854576
申请日：2007-09-13
申请人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
发明人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
IPC分类号： G06F12/00
CPC分类号： G06F13/4027 , G06F11/1076 , G06F2211/1054
摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.
摘要翻译：在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。此外，北桥通过南桥进一步融合到RAID。北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

6. 发明授权

US06694400B1 PCI system controller capable of delayed transaction 有权
标题翻译： PCI系统控制器能够延迟交易
公开(公告)号：US06694400B1
公开(公告)日：2004-02-17
申请号：US09451121
申请日：1999-11-30
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
IPC分类号： G06F1338
CPC分类号： G06F13/4217
摘要： A method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with respect to the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator, indicating that the request has been accepted. When the requested data is ready in the responder, the responder will forward the defer identifier again. The initiator picks up the defer identifier and prepares according to the buffer identifier in it. Then, data transmission between the initiator and the responder begins.
摘要翻译：在PCI系统及其相关设备上进行延迟数据交易的方法。延迟数据事务使用PCI系统在启动器和应答器之间传输数据。启动器和应答器都与PCI总线相连。 PCI系统中的延迟事务包括多个步骤。首先，启动器将发出使用PCI总线的请求，以便可以对响应者进行数据传输。如果响应者接受请求但不能足够快地保护所请求的数据，则响应者将生成对应于请求的发起者的延迟标识符。接下来，由响应者生成的停止信号和延迟标识符将被返回给启动器，指示该请求已被接受。当请求的数据在响应者中准备就绪时，响应者将再次转发延迟标识符。发起人拿起延迟标识符，并根据缓冲区标识符进行准备。然后，启动器和应答器之间的数据传输开始。

7. 发明授权

US06549964B1 Delayed transaction method and device used in a PCI system 有权
公开(公告)号：US06549964B1
公开(公告)日：2003-04-15
申请号：US09451820
申请日：1999-11-30
申请人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
发明人： Jiin Lai , Chau-Chad Tsai , Chen-Ping Yang , Sheng-Chang Peng , Tse-Hsien Wang
IPC分类号： G06F1300
CPC分类号： G06F13/4226
摘要： A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not immediately respond to the first and second request, the responder generates a first and a second defer identifier corresponding to the initiator, respectively. When data transfer between the responder and the initiator corresponding to the first request is completed and data is ready for transfer corresponding to the second request, the responder immediately issues a second buffer identifier along with the data requested corresponding to the second request. Thus, data transfer between the initiator and the responder based on the second buffer identifier corresponding to the second request can proceed.

8. 发明授权

US06941398B2 Processing method, chip set and controller for supporting message signaled interrupt 有权
标题翻译：处理方法，芯片组和控制器支持消息信号中断
公开(公告)号：US06941398B2
公开(公告)日：2005-09-06
申请号：US09826784
申请日：2001-04-04
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Min-Hung Chen , Meng-Cheng Ku , Huei-Li Chou
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Min-Hung Chen , Meng-Cheng Ku , Huei-Li Chou
IPC分类号： G06F13/24 , G06F13/14
CPC分类号： G06F13/24 , G06F2213/2418
摘要： A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.
摘要翻译：一种处理方法，芯片组和用于支持消息信号中断的控制器。监视PCI总线上的存储器写事务。当在写事务的中断消息中指定的系统存储器的地址位于保留的中断地址的范围时，执行中断服务序列。保留的中断地址位于系统存储器的地址中。因此，要处理的数据和系统指定的消息被写入缓冲器中并且按顺序排列。解决了“写缓冲区延迟”的问题，与PCI总线的级别无关。许多系统指定的消息可以存储在系统存储器中，从而可以在相同的中断服务程序中处理来自不同外设组件的多个系统消息信号中断。

9. 发明申请

US20080104320A1 CHIPSET AND NORTHBRIDGE WITH RAID ACCESS 有权
标题翻译： CHIPSET和北桥与RAID访问
公开(公告)号：US20080104320A1
公开(公告)日：2008-05-01
申请号：US11854576
申请日：2007-09-13
申请人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
发明人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
IPC分类号： G06F12/02
CPC分类号： G06F13/4027 , G06F11/1076 , G06F2211/1054
摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.
摘要翻译：在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。此外，北桥通过南桥进一步融合到RAID。北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

10. 发明授权

US07136955B2 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US07136955B2
公开(公告)日：2006-11-14
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/00 , G06F13/20 , G06F13/36
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

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