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1. 发明申请

US20120187406A1 THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY APPARATUS USING THE SAME AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管基板和使用其的显示装置及其制造方法
公开(公告)号：US20120187406A1
公开(公告)日：2012-07-26
申请号：US13349338
申请日：2012-01-12
申请人： Chi-Che TSAI , Wei-Yen WU , Po-Ching LIN
发明人： Chi-Che TSAI , Wei-Yen WU , Po-Ching LIN
IPC分类号： H01L33/08 , H01L21/8234 , H01L27/12
CPC分类号： H01L27/1218
摘要： A thin film transistor substrate, a display apparatus using the same and a manufacturing method thereof are provided. The display apparatus includes a thin film transistor substrate, a top substrate and a display medium layer. The thin film transistor substrate includes a composite plate and several thin film transistors. The composite plate includes a core material structure and two insulation structures. The core material structure includes a metal layer. The two insulation structures are respectively disposed at two sides of the core material structure so as to sandwich the core material structure therebetween. The thin film transistors are disposed on the composite plate. The display medium layer is disposed between the thin film transistor substrate and the top substrate.
摘要翻译：提供薄膜晶体管基板，使用其的显示装置及其制造方法。显示装置包括薄膜晶体管基板，顶部基板和显示介质层。薄膜晶体管基板包括复合板和几个薄膜晶体管。复合板包括芯材结构和两个绝缘结构。芯材结构包括金属层。两个绝缘结构分别设置在芯材结构的两侧，从而将芯材结构夹在其间。薄膜晶体管设置在复合板上。显示介质层设置在薄膜晶体管基板和顶层基板之间。

2. 发明申请

US20060206644A1 Method of hot switching data transfer rate on bus 有权
公开(公告)号：US20060206644A1
公开(公告)日：2006-09-14
申请号：US11433195
申请日：2006-05-11
申请人： Chau-Chad Tsai , Chi-Che Tsai , Chih-kuo Kao
发明人： Chau-Chad Tsai , Chi-Che Tsai , Chih-kuo Kao
IPC分类号： G06F13/42
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.

3. 发明授权

US06934789B2 Interface, structure and method for transmitting data of PCI bus which uses bus request signal for judging whether a device supporting dual transmission mode 有权
标题翻译：用于发送PCI总线数据的接口，结构和方法，该总线使用总线请求信号来判断是否支持双传输模式的设备
公开(公告)号：US06934789B2
公开(公告)日：2005-08-23
申请号：US09894684
申请日：2001-06-27
申请人： Sheng-Chang Peng , Chau-Chad Tsai , Hsuan-Yi Wang , Chi-Che Tsai
发明人： Sheng-Chang Peng , Chau-Chad Tsai , Hsuan-Yi Wang , Chi-Che Tsai
IPC分类号： G06F13/42 , G06F13/38
CPC分类号： G06F13/423
摘要： A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a multiplexer, a strobe generator, and a data distributor. The strobe generator utilizes the bus request signal and bus grant signal to transmit a data strobe signal in response to the PCI clock. According to the rising edge and falling edge of the data strobe signal, the data distributor retrieves data according to the data strobe signal. Further, the invention is compatible with the original PCI bus and allows the PCI bus to transmit data with a dual speed.
摘要翻译：公开了一种用于发送PCI总线的数据的总线数据接口，结构和方法。总线数据接口包括高位发送缓冲器，低位发送缓冲器，复用器，选通发生器和数据分配器。选通发生器利用总线请求信号和总线许可信号来响应于PCI时钟发送数据选通信号。根据数据选通信号的上升沿和下降沿，数据分配器根据数据选通信号检索数据。此外，本发明与原始PCI总线兼容，并允许PCI总线以双速传输数据。

4. 发明授权

US06925517B2 Bus for supporting plural signal line configurations and switch method thereof 有权
标题翻译：用于支持多信号线配置的总线及其切换方法
公开(公告)号：US06925517B2
公开(公告)日：2005-08-02
申请号：US10249361
申请日：2003-04-03
申请人： Sheng-Chang Peng , Chau-Chad Tsai , Chih-kuo Kao , Chi-Che Tsai
发明人： Sheng-Chang Peng , Chau-Chad Tsai , Chih-kuo Kao , Chi-Che Tsai
IPC分类号： H04L5/16 , G06F13/14 , G06F13/40
CPC分类号： H04L5/16
摘要： A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.
摘要翻译：用于支持多个信号线配置的总线及其切换方法，用于在控制芯片之间的总线中操作以保持其操作灵活性。当控制芯片之间的数据传输负载适用于双向传输时，选择双向传输的信号线配置。当双向传输方向频繁切换时，选择其他信号线配置。也就是说，总线信号线分为两部分，每个部分负责每个单向的数据传输，以避免影响传输性能的转向周期。

5. 发明授权

US06721833B2 Arbitration of control chipsets in bus transaction 有权
标题翻译：总线交易中控制芯片组的仲裁
公开(公告)号：US06721833B2
公开(公告)日：2004-04-13
申请号：US09735412
申请日：2000-12-12
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
IPC分类号： G06F1336
CPC分类号： G06F13/36
摘要： A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.
摘要翻译：一种控制芯片组内的总线仲裁方法，控制芯片组还包括第一控制芯片和第二控制芯片，数据通过总线在第一和第二控制芯片之间传输，总线包括双向总线第一控制芯片通常控制使用总线的权限，但第二个控制芯片具有使用总线的优先级。伴随总线规格无等待周期，仲裁权限使用总线可以快速，毫无错误地完成。因此，不需要GNT信号线，仲裁时间缩短。

6. 发明授权

US06718400B1 Data accessing system with an access request pipeline and access method thereof 有权
标题翻译：具有访问请求流水线的数据访问系统及其访问方法
公开(公告)号：US06718400B1
公开(公告)日：2004-04-06
申请号：US09715472
申请日：2000-11-17
申请人： Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
发明人： Chau-Chad Tsai , Chen-Ping Yang , Chi-Che Tsai
IPC分类号： G06F300
CPC分类号： G06F13/161
摘要： A PCI data accessing system with a read request pipeline and an application method thereof are provided. The PCI data accessing system has a PCI master device, a memory module, and a PCI control device. The PCI master device issues a first read request, and the PCI control device converts the first read request to a second read request divided into a first part and a second part. Each part of the second request requests one line data, i.e. 64 bits data. The memory module stores data requested by the PCI master device. Moreover, there is no latency time between data for the first part and the second part returned from the memory module.
摘要翻译：提供了具有读取请求流水线的PCI数据访问系统及其应用方法。 PCI数据访问系统具有PCI主设备，存储器模块和PCI控制设备。 PCI主设备发出第一读请求，并且PCI控制设备将第一读请求转换为分为第一部分和第二部分的第二读请求。第二请求的每个部分请求一行数据，即64位数据。存储器模块存储由PCI主设备请求的数据。此外，在从存储器模块返回的第一部分和第二部分的数据之间没有等待时间。

7. 发明授权

US06684284B1 Control chipset, and data transaction method and signal transmission devices therefor 有权
标题翻译：控制芯片组，数据交易方法及信号传输装置
公开(公告)号：US06684284B1
公开(公告)日：2004-01-27
申请号：US09718811
申请日：2000-11-22
申请人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
发明人： Jiin Lai , Chau-Chad Tsai , Sheng-Chang Peng , Chi-Che Tsai
IPC分类号： G06F944
CPC分类号： G06F13/4027
摘要： A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the status of the buffers within another control chips. When a control chip asserts a command, the corresponding data must be ready in advance. Therefore, the signal line for providing the waiting status, data transaction cycle and stop/retry protocol can be omitted. Accordingly, commands or data can be continuously transmitted without waiting, stop or retry, the performance is improved.
摘要翻译：控制芯片之间的数据交易方法。控制芯片组的控制芯片的数据缓冲器具有固定的尺寸和数量。此外，读/写确认命令根据读/写命令依次被断言，通过该命令，控制芯片可以检测另一个控制芯片内的缓冲器的状态。当控制芯片发出命令时，相应的数据必须提前准备就绪。因此，可以省略用于提供等待状态，数据事务周期和停止/重试协议的信号线。因此，可以连续发送命令或数据，而无需等待，停止或重试，提高性能。

8. 发明授权

US08767164B2 Thin film transistor substrate and display apparatus using the same and manufacturing method thereof 有权
标题翻译：薄膜晶体管基板及使用其的显示装置及其制造方法
公开(公告)号：US08767164B2
公开(公告)日：2014-07-01
申请号：US13349338
申请日：2012-01-12
申请人： Chi-Che Tsai , Wei-Yen Wu , Po-Ching Lin
发明人： Chi-Che Tsai , Wei-Yen Wu , Po-Ching Lin
IPC分类号： G02F1/1333
CPC分类号： H01L27/1218
摘要： A thin film transistor substrate, a display apparatus using the same and a manufacturing method thereof are provided. The display apparatus includes a thin film transistor substrate, a top substrate and a display medium layer. The thin film transistor substrate includes a composite plate and several thin film transistors. The composite plate includes a core material structure and two insulation structures. The core material structure includes a metal layer. The two insulation structures are respectively disposed at two sides of the core material structure so as to sandwich the core material structure therebetween. The thin film transistors are disposed on the composite plate. The display medium layer is disposed between the thin film transistor substrate and the top substrate.
摘要翻译：提供薄膜晶体管基板，使用其的显示装置及其制造方法。显示装置包括薄膜晶体管基板，顶部基板和显示介质层。薄膜晶体管基板包括复合板和几个薄膜晶体管。复合板包括芯材结构和两个绝缘结构。芯材结构包括金属层。两个绝缘结构分别设置在芯材结构的两侧，从而将芯材结构夹在其间。薄膜晶体管设置在复合板上。显示介质层设置在薄膜晶体管基板和顶层基板之间。

9. 发明申请

US20130132619A1 METHOD FOR REDUCING TRANSMISSION LATENCY AND CONTROL MODULE THEREOF 审中-公开
标题翻译：减少传输延迟的方法及其控制模块
公开(公告)号：US20130132619A1
公开(公告)日：2013-05-23
申请号：US13663479
申请日：2012-10-30
申请人： Wei-Yun Chang , Ying-Hung Tang , Chi-Che Tsai , Shu-Tzu Wang
发明人： Wei-Yun Chang , Ying-Hung Tang , Chi-Che Tsai , Shu-Tzu Wang
IPC分类号： G06F3/00
CPC分类号： G06F13/10
摘要： A method for reducing transmission latency and a control module thereof are operated inside a host and at an external USB device. The method includes following steps: when the host receives an NRDY packet, storing a first data segment to be transferred by the host at the buffer storage unit inside the host; when the host receives an ERDY packet, capturing the first data segment stored at the buffer storage unit; and transferring the first data segment to the external USB device.
摘要翻译：一种用于减少传输延迟的方法及其控制模块在主机内和在外部USB设备上操作。该方法包括以下步骤：当主机接收到NRDY分组时，将主机要传送的第一数据段存储在主机内的缓冲存储单元上; 当主机接收到ERDY分组时，捕获存储在缓冲存储单元的第一数据段; 并将第一数据段传送到外部USB设备。

10. 发明授权

US06678771B1 Method of adjusting an access sequencing scheme for a number of PCI- compliant units coupled to a PCI bus system 有权
标题翻译：调整与PCI总线系统耦合的多个PCI兼容单元的接入排序方案的方法
公开(公告)号：US06678771B1
公开(公告)日：2004-01-13
申请号：US09687225
申请日：2000-10-13
申请人： Chau-Chad Tsai , Wen-Hao Chuang , Chi-Che Tsai
发明人： Chau-Chad Tsai , Wen-Hao Chuang , Chi-Che Tsai
IPC分类号： G06F100
CPC分类号： G06F13/423
摘要： A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units are associated respectively with a set of request signals that allow these PCI-compliant units to request the use of the PCI bus system for data transfer. The access sequencing scheme includes a first-layer access sequence loop and a second-layer access sequence loop, with the first-layer access sequence loop having a higher priority over the second-layer access sequence loop The request signals are assigned to either the first-layer access sequence loop or the second-layer access sequence loop in a predetermined manner. The user can change the assignment of a certian request signal from one loop to the other through PC's BIOS (Basic Input/Output System), so as to allow the associated PCI-compliant unit to have a higher priority level to the use of the PCI bus system.
摘要翻译：一种用于调整与计算机系统上的PCI总线系统耦合的多个PCI（外围组件互连）兼容单元的接入排序方案的方法。这些PCI兼容单元分别与一组请求信号相关联，这些请求信号允许这些PCI兼容单元请求使用PCI总线系统进行数据传输。接入排序方案包括第一层接入序列循环和第二层接入序列循环，其中第一层接入序列循环具有比第二层接入序列循环更高的优先权。请求信号被分配给第一层层次访问序列循环或第二层访问序列循环。用户可以通过PC的BIOS（基本输入/输出系统）通过PC的BIOS（基本输入/输出系统）将一个循环的一个循环的分配更改为另一个循环，从而允许相关的PCI兼容单元对PCI的使用具有更高的优先级总线系统。

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