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1. 发明授权

US07594058B2 Chipset supporting a peripheral component interconnection express (PCI-E) architecture 有权
标题翻译：芯片组支持外围组件互连快速（PCI-E）架构
公开(公告)号：US07594058B2
公开(公告)日：2009-09-22
申请号：US11267498
申请日：2005-11-07
申请人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
发明人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.
摘要翻译：使用PCI-E架构的本计算系统包括至少一个第一PCI-E端口，第一端口仲裁器，第一URD逻辑，微处理器，DARD逻辑和设备仲裁器。第一个端口仲裁器从第一个PCI-E端口接收数据。第一URD逻辑耦合到所述第一端口仲裁器。第一个URD逻辑包括板载范围表和PCI-E设备范围表，用于检测板上访问或对等访问的数据。微处理器接收并处理来自用于所述板载存取的第一URD逻辑的数据。 DARD逻辑从微处理器接收数据。 DARD逻辑解码数据的下游请求的设备范围。设备仲裁器耦合到DARD逻辑和第一个URD逻辑，用于将数据分配到第一个PCI-E端口之一。

2. 发明申请

US20070106826A1 Method and computer system using PCI-Express 有权
标题翻译：使用PCI-Express的方法和计算机系统
公开(公告)号：US20070106826A1
公开(公告)日：2007-05-10
申请号：US11267498
申请日：2005-11-07
申请人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
发明人： Peter Chia , Chad Tsai , Jiin Lai , Edward Su , Chih-Kuo Kao
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.
摘要翻译：使用PCI-E架构的本计算系统包括至少一个第一PCI-E端口，第一端口仲裁器，第一URD逻辑，微处理器，DARD逻辑和设备仲裁器。第一个端口仲裁器从第一个PCI-E端口接收数据。第一URD逻辑耦合到所述第一端口仲裁器。第一个URD逻辑包括板载范围表和PCI-E设备范围表，用于检测板上访问或对等访问的数据。微处理器接收并处理来自用于所述板载存取的第一URD逻辑的数据。 DARD逻辑从微处理器接收数据。 DARD逻辑解码数据的下游请求的设备范围。设备仲裁器耦合到DARD逻辑和第一个URD逻辑，用于将数据分配到第一个PCI-E端口之一。

3. 发明申请

US20060085606A1 Method and Related Apparatus for Internal Data Accessing of Computer System 有权
标题翻译：计算机系统内部数据访问方法及相关装置
公开(公告)号：US20060085606A1
公开(公告)日：2006-04-20
申请号：US11162407
申请日：2005-09-09
申请人： Andrew Su , Jiin Lai , Chad Tsai
发明人： Andrew Su , Jiin Lai , Chad Tsai
IPC分类号： G06F12/00
CPC分类号： G06F13/404
摘要： Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to system memory. Also responses from system memory and CPU will be buffered in the chipset respectively utilizing buffer resources of different virtual channels. By applying accessing routing dispatch, data accessing efficiency efficient will be increased.
摘要翻译：用于计算机系统的内部数据访问的方法和相关装置。在计算机系统中，外设可以通过或不侦听中央处理单元（CPU）来发出对系统内存空间的访问请求。在使用支持多个虚拟信道的芯片组服务于单个虚拟信道的外设的同时，本发明根据其窥探/非窥探属性将访问请求分配给不同的处理队列，使得读/非窥探请求被直接路由到系统存储器。来自系统存储器和CPU的响应也将分别利用不同虚拟通道的缓冲资源在芯片组中进行缓冲。通过应用访问路由调度，将提高数据访问效率。

4. 发明授权

US07472232B2 Method and related apparatus for internal data accessing of computer system 有权
标题翻译：计算机系统内部数据访问方法及相关装置
公开(公告)号：US07472232B2
公开(公告)日：2008-12-30
申请号：US11162407
申请日：2005-09-09
申请人： Andrew Su , Jiin Lai , Chad Tsai
发明人： Andrew Su , Jiin Lai , Chad Tsai
IPC分类号： G06F12/00
CPC分类号： G06F13/404
摘要： Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to a system memory. Also responses from system memory and CPU are buffered in the chipset respectively by utilizing buffer resources of different virtual channels. And by applying accessing routing dispatch, data accessing efficiency can be increased.
摘要翻译：用于计算机系统的内部数据访问的方法和相关装置。在计算机系统中，外设可以通过或不侦听中央处理单元（CPU）来发出对系统内存空间的访问请求。在使用支持多个虚拟通道的芯片组服务于单个虚拟信道的外设的同时，本发明根据其窥探/非窥探属性将访问请求分配给不同的处理队列，使得读取/非窥探请求被直接路由到系统记忆。还通过利用不同虚拟通道的缓冲资源，分别在芯片组中缓冲来自系统存储器和CPU的响应。通过应用访问路由调度，可以提高数据访问效率。

5. 发明申请

US20070011390A1 METHOD AND RELATED APPARATUS FOR CONTROLLING A PERIPHERAL DEVICE TO TRANSFER DATA TO A BUS 审中-公开
标题翻译：用于控制外部设备以将数据传送到总线的方法和相关装置
公开(公告)号：US20070011390A1
公开(公告)日：2007-01-11
申请号：US11531282
申请日：2006-09-13
申请人： Jiin Lai , Chad Tsai , Ju Zhang , Andrew Chuang , Andrew Su
发明人： Jiin Lai , Chad Tsai , Ju Zhang , Andrew Chuang , Andrew Su
IPC分类号： G06F13/20
CPC分类号： G06F13/385
摘要： A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.
摘要翻译：一种用于控制外围设备将数据传送到总线的方法和相关装置。外围设备具有总线接口电路和控制器。该方法包括将从控制器输出的数据存储到总线接口电路的第一存储块中，利用总线接口电路同时控制第一存储块以将其存储的数据输出到总线并控制总线接口的第二存储块存储从控制器输出的数据的电路，利用总线接口电路来控制第二存储块，将其存储的数据输出到总线。

6. 发明授权

US07124214B2 Method and related apparatus for controlling a peripheral device to transfer data to a bus 有权
标题翻译：用于控制外围设备将数据传送到总线的方法和相关装置
公开(公告)号：US07124214B2
公开(公告)日：2006-10-17
申请号：US10707806
申请日：2004-01-14
申请人： Jiin Lai , Chad Tsai , Ju Zhang , Andrew Chuang , Andrew Su
发明人： Jiin Lai , Chad Tsai , Ju Zhang , Andrew Chuang , Andrew Su
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.
摘要翻译：一种用于控制外围设备将数据传送到总线的方法和相关装置。外围设备具有总线接口电路和控制器。该方法包括将从控制器输出的数据存储到总线接口电路的第一存储块中，利用总线接口电路同时控制第一存储块以将其存储的数据输出到总线并控制总线接口的第二存储块存储从控制器输出的数据的电路，利用总线接口电路来控制第二存储块，将其存储的数据输出到总线。

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