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1. 发明授权

US08781332B2 Optical transceiver module, optical transmission device, and optical transmission method 有权
标题翻译：光收发模块，光传输设备和光传输方式
公开(公告)号：US08781332B2
公开(公告)日：2014-07-15
申请号：US13018548
申请日：2011-02-01
申请人： Jin-Kuan Tang , Jiin Lai
发明人： Jin-Kuan Tang , Jiin Lai
IPC分类号： H04B10/00
CPC分类号： H04B10/40
摘要： An optical transceiver module adapted to a link device includes a connection unit, a driving unit and optical transmitting and receiving units. The connection unit, to be coupled with the link device, includes an indicating element for generating an indicating signal when the connection unit is coupled with the link device. The driving unit, coupled with the connection unit, receives the indicating signal and outputs a control signal according to the indicating signal. The optical transmitting unit, coupled with the driving unit, receives the control signal for driving the optical transmitting unit to output a first optical signal. The optical receiving unit, coupled with the driving unit, transmits a received second optical signal to the driving unit. An optical transmission device using the optical transceiver module, and an optical transmission method are also disclosed. A link training sequence can be initiated after the connection unit is actually coupled with the link device. Thus, a host cannot enter a disable mode due to error connection.
摘要翻译：适于链接装置的光收发模块包括连接单元，驱动单元和光发射和接收单元。要与链接装置耦合的连接单元包括用于当连接单元与链接装置耦合时产生指示信号的指示元件。与连接单元耦合的驱动单元接收指示信号，并根据指示信号输出控制信号。与驱动单元耦合的光发送单元接收用于驱动光发送单元的控制信号以输出第一光信号。光接收单元与驱动单元耦合，将接收到的第二光信号发送到驱动单元。还公开了使用光收发模块的光传输装置和光传输方法。链路训练序列可以在连接单元实际上与链路设备耦合之后启动。因此，由于错误连接，主机无法进入禁用模式。

2. 发明授权

US08549184B2 USB transaction translator with buffers and a bulk transaction method 有权
标题翻译：具有缓冲区和批量事务方法的USB事务翻译器
公开(公告)号：US08549184B2
公开(公告)日：2013-10-01
申请号：US12959299
申请日：2010-12-02
申请人： Jinkuan Tang , Jiin Lai , Buheng Xu , Hui Jiang
发明人： Jinkuan Tang , Jiin Lai , Buheng Xu , Hui Jiang
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/385
摘要： The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN/OUT bulk transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. In a bulk-IN transaction, before the host sends an IN packet, the controller pre-fetches data and stores the data in the buffers until all the buffers are full or a requested data length has been achieved; the pre-fetched data are then sent to the host after the host sends the IN packet. In a bulk-OUT transaction, the controller stores the data sent from the host in the buffers, and the data are then post-written to the device.
摘要翻译：本发明涉及通用串行总线（USB）事务转换器和相关的IN / OUT批量交易方法。设备接口经由设备总线耦合到设备，并且主机接口通过主机总线耦合到主机，其中主机USB版本高于设备USB版本。配置为存储数据的至少两个缓冲器被布置在设备接口和主机接口之间。控制器交替地将数据存储在缓冲器中。在批量IN事务中，在主机发送IN数据包之前，控制器预取数据并将数据存储在缓冲器中，直到所有缓冲器已满或已达到所请求的数据长度为止; 在主机发送IN数据包之后，将预取的数据发送到主机。在bulk-OUT事务中，控制器将从主机发送的数据存储在缓冲区中，然后将数据写入设备。

3. 发明申请

US20110246681A1 APPARATUS INTEROPERABLE WITH BACKWARD COMPATIBLE OPTICAL USB DEVICE 有权
标题翻译：装置与后置兼容的OPTICAL USB DEVICE相兼容
公开(公告)号：US20110246681A1
公开(公告)日：2011-10-06
申请号：US12818342
申请日：2010-06-18
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/4081 , G06F2213/0042
摘要： An apparatus configured to couple to a universal serial bus (USB) 3.0 connector. The apparatus includes a management controller configured to couple to the USB 3.0 connector. The management controller is configured to detect from behavior on the D+ and D− pins of the USB 3.0 connector whether a device plugged into the USB 3.0 connector is a conventional USB 3.0 device or an optical USB device.
摘要翻译：一种被配置为耦合到通用串行总线（USB）3.0连接器的装置。该装置包括配置成耦合到USB 3.0连接器的管理控制器。管理控制器配置为检测USB 3.0连接器的D +和D-引脚上的行为，连接USB 3.0连接器的设备是传统的USB 3.0设备还是光学USB设备。

4. 发明申请

US20110219272A1 Data Transmission System and Method Thereof 有权
标题翻译：数据传输系统及其方法
公开(公告)号：US20110219272A1
公开(公告)日：2011-09-08
申请号：US12862134
申请日：2010-08-24
申请人： Jiin Lai , Buheng Xu , Jinkuan Tang
发明人： Jiin Lai , Buheng Xu , Jinkuan Tang
IPC分类号： G06F11/08 , G06F13/00 , G06F13/12
CPC分类号： G06F13/385 , G06F11/08 , G06F13/00 , G06F13/12
摘要： A data transmission system is provided. The data transmission system includes a first control circuit coupled to a first device, a translation circuit coupled to the first control circuit and a second control circuit coupled to the translation circuit. The first control circuit decodes a first format data packet sent by the first device. The translation circuit receives the decoded first format data packet and translates the decoded first format data packet into a second format data packet. The second control circuit transmits the second format data packet to a host. A data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device.
摘要翻译：提供数据传输系统。数据传输系统包括耦合到第一设备的第一控制电路，耦合到第一控制电路的平移电路和耦合到转换电路的第二控制电路。第一控制电路解码由第一设备发送的第一格式数据分组。翻译电路接收解码的第一格式数据分组，并将解码的第一格式数据分组转换为第二格式数据分组。第二控制电路将第二格式数据包发送到主机。第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备。

5. 发明申请

US20110066785A1 Memory Management System and Method Thereof 有权
标题翻译：内存管理系统及其方法
公开(公告)号：US20110066785A1
公开(公告)日：2011-03-17
申请号：US12694470
申请日：2010-01-27
申请人： JIAN LI , JIIN LAI , SHAN-NA PANG , ZHI-QIANG HUI , DI DAI
发明人： JIAN LI , JIIN LAI , SHAN-NA PANG , ZHI-QIANG HUI , DI DAI
IPC分类号： G06F12/10 , G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/1036
摘要： A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.
摘要翻译：存储器管理系统和方法包括并使用高速缓冲存储器（例如，表查看缓冲器，TLB），存储器映射表，暂存器缓存和存储器控制器。高速缓存缓冲器被配置为存储多个数据结构。存储器映射表被配置为存储数据结构的多个地址。暂存器缓存被配置为存储数据结构的基址。存储器控制器被配置为控制高速缓冲存储器和暂存器缓存中的读写。这些组件在存储器控制器的控制下一起可操作，以便有效地搜索存储器管理系统中的数据结构。

6. 发明授权

US07805567B2 Chipset and northbridge with raid access 有权
标题翻译：芯片组和北桥与突袭访问
公开(公告)号：US07805567B2
公开(公告)日：2010-09-28
申请号：US11854576
申请日：2007-09-13
申请人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
发明人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
IPC分类号： G06F12/00
CPC分类号： G06F13/4027 , G06F11/1076 , G06F2211/1054
摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.
摘要翻译：在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。此外，北桥通过南桥进一步融合到RAID。北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

7. 发明授权

US07271578B2 Voltage monitoring circuit 有权
标题翻译：电压监控电路
公开(公告)号：US07271578B2
公开(公告)日：2007-09-18
申请号：US11131401
申请日：2005-05-18
申请人： Hung Yi Kuo , Jenny Chen , Jiin Lai
发明人： Hung Yi Kuo , Jenny Chen , Jiin Lai
IPC分类号： G01R17/06
CPC分类号： G01R19/16552
摘要： A voltage monitoring circuit is capable of being integrated into a chip and monitoring the voltage quality. It mainly uses a first waveshaper to receive a voltage signal of a voltage source to be measured, process it to a logic signal, and output to a first logic level transformer. A first digital signal is transformed by the processing and can be recorded by a register such that a managing system can read content of the register through a bus to further determine whether the voltage source has a situation of voltage surge. Similarly, an inverter can be concatenated between a second waveshaper and a second logic level transformer to monitor whether the voltage source has undercurrent pulse. This way, an object of monitoring voltage quality in the chip with a combination of simple analog circuit can be achieved.
摘要翻译：电压监测电路能够集成到芯片中并监测电压质量。它主要使用第一个波形器接收要测量的电压源的电压信号，将其处理为逻辑信号，并输出到第一逻辑电平变压器。第一数字信号通过处理变换，并且可以由寄存器记录，使得管理系统可以通过总线读取寄存器的内容，以进一步确定电压源是否具有电压浪涌的情况。类似地，逆变器可以连接在第二波形与第二逻辑电平变换器之间，以监测电压源是否具有欠电流脉冲。这样，可以实现利用简单模拟电路的组合来监视芯片中的电压质量的目的。

8. 发明授权

US07231309B2 Method and apparatus for testing a bridge circuit 有权
标题翻译：用于测试桥接电路的方法和装置
公开(公告)号：US07231309B2
公开(公告)日：2007-06-12
申请号：US10904047
申请日：2004-10-21
申请人： Biyun Yeh , Victor Wu , Jiin Lai
发明人： Biyun Yeh , Victor Wu , Jiin Lai
IPC分类号： G06F19/00
CPC分类号： G01R31/31725 , G01R31/31727
摘要： A method and an apparatus for testing a bridge circuit. The method includes inputting a first test clock to a first conversion unit for triggering the first conversion unit to transfer a test data to a second conversion unit according to rising edges of the first test clock, inputting a second test clock to the second conversion unit for triggering the second conversion unit to output an output data according to falling edges of the second test clock, and controlling the first test clock and the second test clock so that the rising edges of the second test clock are not synchronized to the rising edges of the first test clock. A frequency of the first test clock is an even multiple of a frequency of the second test clock.
摘要翻译：一种测试桥接电路的方法和装置。该方法包括将第一测试时钟输入到第一转换单元，用于触发第一转换单元根据第一测试时钟的上升沿将测试数据传送到第二转换单元，向第二转换单元输入第二测试时钟触发所述第二转换单元根据所述第二测试时钟的下降沿输出输出数据，并且控制所述第一测试时钟和所述第二测试时钟，使得所述第二测试时钟的上升沿不与所述第二测试时钟的上升沿同步第一个测试时钟。第一测试时钟的频率是第二测试时钟的频率的偶数倍。

9. 发明申请

US20060174142A1 Power management method of north bridge 有权
公开(公告)号：US20060174142A1
公开(公告)日：2006-08-03
申请号：US11215222
申请日：2005-08-30
申请人： Ruei-Ling Lin , Jiin Lai , Hung-Yi Kuo
发明人： Ruei-Ling Lin , Jiin Lai , Hung-Yi Kuo
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.

10. 发明授权

US07032092B2 Memory controller for supporting a plurality of different memory accesse modes 有权
公开(公告)号：US07032092B2
公开(公告)日：2006-04-18
申请号：US10236794
申请日：2002-09-06
申请人： Jiin Lai
发明人： Jiin Lai
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F13/4243
摘要： A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals to process data. The controller can further delay the data for a predetermined time period and capture the same.

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