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1. 发明授权

US07051148B2 Data transmission sequencing method associated with briding device and application system 有权
公开(公告)号：US07051148B2
公开(公告)日：2006-05-23
申请号：US10055558
申请日：2002-01-22
申请人： Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai , Wen-Hao Chuang , Chun-Yuan Su
发明人： Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai , Wen-Hao Chuang , Chun-Yuan Su
IPC分类号： G06F13/36 , G06F13/42
CPC分类号： G06F13/4059
摘要： A data transmission sequencing method is disclosed. A data read operation from a primary bus to a secondary bus can be executed without having to wait for the complete transfer of write data stored in posted write buffer transferring to the primary bus, as long as the secondary bus is not in use. In the mean time of the primary bus issues a read operation to the secondary bus, the secondary bus can issues write operation to the bridging device when the secondary bus is not in use. Similarly, there is no need to wait for the completion of read operation. With this type of data transmission sequencing mechanism, idle sessions in a conventional transmission sequencing method are eliminated leading to a higher data transmission rate.

2. 发明授权

US07136955B2 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US07136955B2
公开(公告)日：2006-11-14
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/00 , G06F13/20 , G06F13/36
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device.
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块。

3. 发明申请

US20050097254A1 Expansion adapter supporting both PCI and AGP device functions 有权
标题翻译：扩展适配器支持PCI和AGP设备功能
公开(公告)号：US20050097254A1
公开(公告)日：2005-05-05
申请号：US10980624
申请日：2004-11-03
申请人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
发明人： Chun-Yuan Su , Jiin Lai , Chau-Chad Tsai , Chi-Che Tsai
IPC分类号： G06F13/36 , G06F13/38
CPC分类号： G06F13/385 , G06F2213/0024
摘要： An expansion adapter is used to communicate both PCI and AGP devices to the north bridge chip of a computer. The expansion adapter includes a first AGP bus control module communicable with the north bridge chip via a first AGP bus, and a second AGP bus control module in communication with the first AGP bus control module, communicable with an AGP device via a second AGP bus. The identifying codes of the first and second AGP bus control modules are set to show no AGP device function in order to allow the AGP device to communicate with the north bridge chip via the expansion adapter. The expansion adapter further includes a PCI bus control module in communication with the PCI device and the first AGP bus control module for controlling data transmission between the first AGP bus control module and the PCI device
摘要翻译：扩展适配器用于将PCI和AGP设备通信到计算机的北桥芯片。扩展适配器包括经由第一AGP总线与北桥芯片通信的第一AGP总线控制模块，以及与第一AGP总线控制模块通信的第二AGP总线控制模块，经由第二AGP总线与AGP设备通信。第一和第二AGP总线控制模块的识别码被设置为不显示AGP设备功能，以便允许AGP设备经由扩展适配器与北桥芯片通信。扩展适配器还包括与PCI设备通信的PCI总线控制模块和用于控制第一AGP总线控制模块和PCI设备之间的数据传输的第一AGP总线控制模块

4. 发明授权

US07805567B2 Chipset and northbridge with raid access 有权
标题翻译：芯片组和北桥与突袭访问
公开(公告)号：US07805567B2
公开(公告)日：2010-09-28
申请号：US11854576
申请日：2007-09-13
申请人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
发明人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
IPC分类号： G06F12/00
CPC分类号： G06F13/4027 , G06F11/1076 , G06F2211/1054
摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.
摘要翻译：在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。此外，北桥通过南桥进一步融合到RAID。北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

5. 发明申请

US20080104320A1 CHIPSET AND NORTHBRIDGE WITH RAID ACCESS 有权
标题翻译： CHIPSET和北桥与RAID访问
公开(公告)号：US20080104320A1
公开(公告)日：2008-05-01
申请号：US11854576
申请日：2007-09-13
申请人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
发明人： Chun-Yuan Su , Chau-Chad Tsai , Jiin Lai
IPC分类号： G06F12/02
CPC分类号： G06F13/4027 , G06F11/1076 , G06F2211/1054
摘要： A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The Northbridge include a RAID accelerator for performing RAID operations according to RAID control commands which are stored in a register.
摘要翻译：在中央处理单元，系统存储器和南桥之间耦合提供RAID访问的北桥。此外，北桥通过南桥进一步融合到RAID。北桥包含RAID加速器，用于根据存储在寄存器中的RAID控制命令进行RAID操作。

6. 发明申请

US20070101026A1 BUS CONTROLLER AND DATA BUFFER SPACE CONFIGURATION METHOD OF THE SAME 审中-公开
标题翻译：总线控制器和数据缓冲器空间配置方法
公开(公告)号：US20070101026A1
公开(公告)日：2007-05-03
申请号：US11538747
申请日：2006-10-04
申请人： Jiin Lai , Chun-Yuan Su , Yuan-Zong Cheng
发明人： Jiin Lai , Chun-Yuan Su , Yuan-Zong Cheng
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4059 , G06F2213/0024
摘要： In a data buffer space configuration method for requesting data from a target device via a bus, a device count of master device coupled to the bus is detected by the operating system. Then, a first data buffer space is configured to the master device if the device count is not greater than a threshold. On the other hand, a second data buffer space is configured to the master device if the device count is greater than the threshold.
摘要翻译：在用于经由总线从目标设备请求数据的数据缓冲器空间配置方法中，操作系统检测耦合到总线的主设备的设备数量。然后，如果设备计数不大于阈值，则将第一数据缓冲区配置给主设备。另一方面，如果设备计数大于阈值，则将第二数据缓冲空间配置到主设备。

7. 发明授权

US07991924B2 Method and system for initializing devices 有权
标题翻译：初始化设备的方法和系统
公开(公告)号：US07991924B2
公开(公告)日：2011-08-02
申请号：US11610631
申请日：2006-12-14
申请人： Chun-Yuan Su , I-Lin Hsieh , Chi-Feng Lin
发明人： Chun-Yuan Su , I-Lin Hsieh , Chi-Feng Lin
IPC分类号： G06F3/00
CPC分类号： G06F1/24
摘要： A system for a first device to initialize a second device is disclosed. The initialization bus is coupled between the first device and the second device. During an initialization period, the first device triggers at least one transmission command through the initialization bus to transmit at least one initial value to the second device via the initialization bus.
摘要翻译：公开了一种用于初始化第二设备的第一设备的系统。初始化总线耦合在第一设备和第二设备之间。在初始化期间，第一设备通过初始化总线触发至少一个发送命令，以经由初始化总线将至少一个初始值发送到第二设备。

8. 发明申请

US20080126783A1 METHOD AND SYSTEM FOR INITIALIZING DEVICES 有权
标题翻译：用于初始化设备的方法和系统
公开(公告)号：US20080126783A1
公开(公告)日：2008-05-29
申请号：US11610631
申请日：2006-12-14
申请人： Chun-Yuan Su , I-Lin Hsieh , Chi-Feng Lin
发明人： Chun-Yuan Su , I-Lin Hsieh , Chi-Feng Lin
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： A system for a first device to initialize a second device is disclosed. The initialization bus is coupled between the first device and the second device. During an initialization period, the first device triggers at least one transmission command through the initialization bus to transmit at least one initial value to the second device via the initialization bus.
摘要翻译：公开了一种用于初始化第二设备的第一设备的系统。初始化总线耦合在第一设备和第二设备之间。在初始化期间，第一设备通过初始化总线触发至少一个发送命令，以经由初始化总线将至少一个初始值发送到第二设备。

9. 发明申请

US20070130411A1 DATA BUFFERING METHOD 有权
标题翻译：数据缓冲方法
公开(公告)号：US20070130411A1
公开(公告)日：2007-06-07
申请号：US11550263
申请日：2006-10-17
申请人： Chun-Yuan Su
发明人： Chun-Yuan Su
IPC分类号： G06F13/36
CPC分类号： G06F13/423
摘要： In a data processing and buffering method, at least one read cycles are asserted to obtain at least one data, respectively, wherein each of the data includes at least one sub data and each data is specified with an address pointer and an enable bit array. When a certain sub data is received, the corresponding bit of the enable bit array is enabled. The corresponding sub data of the enabled bit is indicated by the address pointer.
摘要翻译：在数据处理和缓冲方法中，断言至少一个读周期来获得至少一个数据，其中每个数据包括至少一个子数据，并且每个数据由地址指针和使能位阵列指定。当接收到某个子数据时，使能位阵列的相应位被使能。使能位的相应子数据由地址指针指示。

10. 发明申请

US20130222017A1 RESET DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME 审中-公开
标题翻译：复位装置和具有该装置的电子系统
公开(公告)号：US20130222017A1
公开(公告)日：2013-08-29
申请号：US13489259
申请日：2012-06-05
申请人： Chun-Yuan Su , Ching-Ming Huang
发明人： Chun-Yuan Su , Ching-Ming Huang
IPC分类号： H03L7/00
CPC分类号： G06F1/24
摘要： An electronic system is provided. The electronic system comprises a power device and a reset device. The power device provides power to the electronic system. The reset device comprises a wireless signal generator, a wireless signal receiver and a control module. The wireless signal generator generates a wireless signal. The wireless signal receiver receives the wireless signal and generates a control signal in response. The control module is electrically connected to the wireless signal receiver to activate a reset mechanism of the control module or reset the power device upon reception of the control signal from the wireless signal receiver.
摘要翻译：提供电子系统。电子系统包括电源装置和复位装置。电力设备为电子系统提供电力。复位装置包括无线信号发生器，无线信号接收器和控制模块。无线信号发生器产生无线信号。无线信号接收机接收无线信号并产生响应的控制信号。控制模块电连接到无线信号接收器，以在接收到来自无线信号接收机的控制信号时启动控制模块的复位机构或复位功率器件。

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