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1. 发明授权

US06643747B2 Processing requests to efficiently access a limited bandwidth storage area 有权
公开(公告)号：US06643747B2
公开(公告)日：2003-11-04
申请号：US09751625
申请日：2000-12-27
申请人： Per H. Hammarlund , Douglas M. Carmean , Michael D. Upton
发明人： Per H. Hammarlund , Douglas M. Carmean , Michael D. Upton
IPC分类号： G06F1200
CPC分类号： G06F12/0857
摘要： A request received from a requester to access a processor cache or register file or the like is buffered, by storing requestor identification, request type, address, and a status of the request. This buffered request may be forwarded to the cache if it has the highest priority among a number of buffered requests that also wish to access the cache. The priority is a function of at least the requestor identification, the requester type, and the status of the request. For buffered requests which include a read, the buffered request is deleted after, not before, receiving an indication that the requestor has received the data read from the cache.

2. 发明授权

US06981129B1 Breaking replay dependency loops in a processor using a rescheduled replay queue 失效
标题翻译：使用重新安排的重播队列在处理器中重新播放依赖循环
公开(公告)号：US06981129B1
公开(公告)日：2005-12-27
申请号：US09705668
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重新安排的重播队列在处理器中重新播放依赖循环。所述处理器包括用于接收多个指令的重放队列，以及执行所述多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。检查器耦合到执行单元以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

3. 发明授权

US06877086B1 Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter 失效
标题翻译：使用重放队列和计数器在处理器中重新安排多个微操作的方法和装置
公开(公告)号：US06877086B1
公开(公告)日：2005-04-05
申请号：US09705678
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重放队列在处理器中重新安排多个微操作。处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地安排执行指令并将每个指令分派到执行单元。检查器耦合到执行单元以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

4. 发明授权

US07797683B2 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor 有权
标题翻译：从处理器中同时处理的物理线程的数量解耦逻辑线程数
公开(公告)号：US07797683B2
公开(公告)日：2010-09-14
申请号：US10745527
申请日：2003-12-29
申请人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
发明人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
IPC分类号： G06F9/44
CPC分类号： G06F9/485 , G06F9/3851
摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.
摘要翻译：管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。

5. 发明授权

US06370625B1 Method and apparatus for lock synchronization in a microprocessor system 有权
标题翻译：用于微处理器系统中锁同步的方法和装置
公开(公告)号：US06370625B1
公开(公告)日：2002-04-09
申请号：US09474698
申请日：1999-12-29
申请人： Douglas M. Carmean , Harish Kumar , Brent E. Lince , Michael D. Upton , Zhongying Zhang
发明人： Douglas M. Carmean , Harish Kumar , Brent E. Lince , Michael D. Upton , Zhongying Zhang
IPC分类号： G06F1318
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/3842
摘要： A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.
摘要翻译：一种控制一个或多个处理器的操作的方法包括将具有其中存储的数据的存储器位置的所有权授予第一处理器，并以原子方式由第一处理器执行读取操作，以将数据从存储器位置加载到注册，修改操作以修改寄存器中的数据，以及写入操作，以将数据从寄存器存储到存储器位置。当读取，修改和写入操作由第一处理器执行时，该方法还防止由第二处理器指向数据的其他操作，反之亦然。在执行读取，修改和写入操作之后释放内存位置的所有权，以便允许第一或第二处理器执行后续的原子操作。

6. 发明申请

US20140111629A1 SYSTEM FOR DYNAMIC PROJECTION OF MEDIA 审中-公开
标题翻译：动态投影系统
公开(公告)号：US20140111629A1
公开(公告)日：2014-04-24
申请号：US13795295
申请日：2013-03-12
申请人： Margaret Morris , Douglas M. Carmean
发明人： Margaret Morris , Douglas M. Carmean
IPC分类号： H04N9/31
CPC分类号： H04N9/31 , G06Q30/0261 , G06Q30/0267 , G06Q30/0268 , H04L12/2809 , H04L12/2812 , H04L67/22 , H04L2012/2841 , H04L2012/2849 , H04N9/3194 , H04N21/25816 , H04N21/25841 , H04N21/2668 , H04N21/2743 , H04N21/4122 , H04N21/41407 , H04N21/41415 , H04N21/4223 , H04N21/44218 , H04N21/478 , H04N21/4788 , H04W4/021 , H04W4/21 , H04W4/80
摘要： A system for presenting an image on a user in a social setting includes an image projection system configured to detect the presence of a user via their mobile device when the user comes within a predefined proximity, such as within a real-world social setting (e.g., coffeehouse, bar, club, etc.). The image projection system is further configured to access a social network platform and detect media content associated with the user, particularly media content that the user has shared on the social network platform via their mobile device. The image projection system is further configured to project media content onto the user's body, clothing and/or personal items via a projector and dynamically adapt projection of the media content in the event the user moves within the social setting.
摘要翻译：用于在社交设置中在用户上呈现图像的系统包括：图像投影系统，被配置为当用户进入预定义的接近度期间（例如在真实世界的社会环境中）（例如，用户）在其移动设备中检测用户的存在。，咖啡馆，酒吧，俱乐部等）。图像投影系统还被配置为访问社交网络平台并检测与用户相关联的媒体内容，特别是用户已经通过其移动设备在社交网络平台上共享的媒体内容。图像投影系统还被配置为经由投影仪将媒体内容投影到用户的身体，衣服和/或个人物品上，并且在用户在社交环境中移动的情况下动态地调整媒体内容的投影。

7. 发明授权

US08347066B2 Replay instruction morphing 有权
标题翻译：重播指示变形
公开(公告)号：US08347066B2
公开(公告)日：2013-01-01
申请号：US11069004
申请日：2005-02-28
申请人： Douglas M. Carmean , David J. Sager , Thomas F. Toll , Karol F. Menezes
发明人： Douglas M. Carmean , David J. Sager , Thomas F. Toll , Karol F. Menezes
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.
摘要翻译：重播指示变形。所公开的装置包括执行指令的执行单元。如果执行单元错误地执行指令，则重放系统重放改变的指令。

8. 发明授权

US06366984B1 Write combining buffer that supports snoop request 有权
标题翻译：写入组合缓冲区，支持窥探请求
公开(公告)号：US06366984B1
公开(公告)日：2002-04-02
申请号：US09309726
申请日：1999-05-11
申请人： Douglas M. Carmean , Brent E. Lince
发明人： Douglas M. Carmean , Brent E. Lince
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , G06F12/0831 , G06F12/0897
摘要： A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus.
摘要翻译：支持窥探请求的写入组合缓冲器包括第一缓存存储器和第二高速缓冲存储器。该装置还包括耦合到第一和第二高速缓存存储器的组合缓冲器，以组合来自多个存储操作的数据。多个存储操作中的每一个都是高速缓存线的至少一部分，并且可以响应于在该设备外部发起的请求来窥探该写入组合缓冲器。

9. 发明授权

US07158911B2 Methods and apparatus for thermal management of an integrated circuit die 有权
标题翻译：集成电路管芯的热管理方法和装置
公开(公告)号：US07158911B2
公开(公告)日：2007-01-02
申请号：US10821822
申请日：2004-04-09
申请人： Stephen H. Gunther , Frank Binns , Jack D. Pippin , Linda J. Rankin , Edward A. Burton , Douglas M. Carmean , John M. Bauer
发明人： Stephen H. Gunther , Frank Binns , Jack D. Pippin , Linda J. Rankin , Edward A. Burton , Douglas M. Carmean , John M. Bauer
IPC分类号： H01L31/58
CPC分类号： G06F1/206 , G01K7/015 , G06F1/3237 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/128 , Y02D10/16 , Y02D10/172
摘要： An integrated, on-chip thermal management system providing closed-loop temperature control of an IC device and methods of performing thermal management of an IC device. The thermal management system comprises a temperature detection element, a power modulation element, a control element, and a visibility element. The temperature detection element includes a temperature sensor for detecting die temperature. The power modulation element may reduce the power consumption of an IC device by directly lowering the power consumption of the IC device, by limiting the speed at which the IC device executes instructions, by limiting the number of instructions executed by the IC device, or by a combination of these techniques. The control element allows for control over the behavior of the thermal management system, and the visibility element allows external devices to monitor the status of the thermal management system.
摘要翻译：集成的片上热管理系统，提供IC器件的闭环温度控制和执行IC器件热管理的方法。热管理系统包括温度检测元件，功率调制元件，控制元件和可见度元件。温度检测元件包括用于检测管芯温度的温度传感器。功率调制元件可以通过直接降低IC器件的功耗来限制IC器件执行指令的速度，通过限制由IC器件执行的指令的数量，或通过这些技术的组合。控制元件允许控制热管理系统的行为，并且可见性元件允许外部设备监视热管理系统的状态。

10. 发明授权

US06687809B2 Maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses 有权
标题翻译：通过检查未接收的加载指令的负载地址来监视存储地址来维护处理器的顺序
公开(公告)号：US06687809B2
公开(公告)日：2004-02-03
申请号：US10279601
申请日：2002-10-24
申请人： Muntaquim F. Chowdhury , Douglas M. Carmean
发明人： Muntaquim F. Chowdhury , Douglas M. Carmean
IPC分类号： G06F938
CPC分类号： G06F9/3851 , G06F9/3834
摘要： An apparatus in a first processor includes a first data structure to store addresses of store instruction dispatched during a last predetermined number of cycles. The apparatus further includes logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure. The apparatus still further includes logic to replay to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.
摘要翻译：第一处理器中的装置包括第一数据结构，用于存储在最后预定次数周期期间调度的存储指令的地址。该装置还包括用于确定正在执行的加载指令的加载地址是否与第一数据结构中的存储地址之一匹配的逻辑。如果各个加载指令的加载地址与第一数据结构中的存储地址匹配，则该装置还包括重放相应加载指令的逻辑。

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