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1. 发明授权

US06781588B2 Texture engine memory access synchronizer 失效
公开(公告)号：US06781588B2
公开(公告)日：2004-08-24
申请号：US09964802
申请日：2001-09-28
申请人： Gavril Margittai , Zeev Sperber , Gabi Malka
发明人： Gavril Margittai , Zeev Sperber , Gabi Malka
IPC分类号： G06F1318
CPC分类号： G06T15/04
摘要： An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

2. 发明授权

US06560667B1 Handling contiguous memory references in a multi-queue system 有权
标题翻译：处理多队列系统中的连续内存引用
公开(公告)号：US06560667B1
公开(公告)日：2003-05-06
申请号：US09473112
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F1318
CPC分类号： G06F13/1642
摘要： A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references, such that the arbiter services a same queue until the chaining bit is cleared.
摘要翻译：用于随机存取存储器的控制器具有控制逻辑，包括检测未完成存储器引用状态的仲裁器。控制器从存储器引用的多个队列中的一个队列中选择存储器引用。控制逻辑响应于存储器参考链接位，当设置允许连续存储器引用的特殊处理时，仲裁器服务相同的队列，直到链接位被清除。

3. 发明授权

US06496899B1 Disk scheduling system with bounded request reordering 有权
标题翻译：磁盘调度系统有限请求重新排序
公开(公告)号：US06496899B1
公开(公告)日：2002-12-17
申请号：US09514485
申请日：2000-02-28
申请人： Michael A. DeMoney
发明人： Michael A. DeMoney
IPC分类号： G06F1318
CPC分类号： H04N21/23106 , G06F3/061 , G06F3/0659 , G06F3/0689 , H04N21/2312 , H04N21/2326
摘要： A disk scheduling system with bounded request reordering. Disk access requests may be performed during traversals of a disk head across a disk. Each traversal may have a specified direction of motion. A plurality of disk accesses may be performed during a disk head traversal. The overall number of disk access requests for a given disk head traversal may be limited to a maximum number N. By limiting the number of disk requests for each traversal, a bound may effectively be placed on the amount of time it takes to satisfy any single disk request.
摘要翻译：具有有限请求重新排序的磁盘调度系统。磁盘访问请求可以在跨磁盘跨越磁盘头时执行。每个遍历可能具有指定的运动方向。可以在磁盘头遍历期间执行多个磁盘访问。给定磁盘头遍历的磁盘访问请求的总数可能被限制为最大数量N.通过限制每个遍历的磁盘请求数，绑定可以有效地放置在满足任何单个磁盘请求。

4. 发明授权

US06415354B1 Pipelined methods and apparatus for weight selection and content addressable memory searches 有权
标题翻译：用于权重选择和内容可寻址存储器搜索的流水线方法和装置
公开(公告)号：US06415354B1
公开(公告)日：2002-07-02
申请号：US09354684
申请日：1999-07-15
申请人： Alexander Joffe , Oran Uzrad-Nali , Simon H. Milner
发明人： Alexander Joffe , Oran Uzrad-Nali , Simon H. Milner
IPC分类号： G06F1318
CPC分类号： G11C15/00
摘要： When a search key is supplied to a content addressable memory (CAM), the CAM signals indicate which CAM entries have matched the key. These signals are provided to a weight array to select the entry of the highest priority. Each entry's priority is indicated by a weight in the weight array. The weight array processing is pipelined. In pipeline stage 0, the most significant bits (bits 0) of the weights are examined, and the highest priorities are selected based on the most significant bits. At pipeline stage 1, the next most significant bits (bits 1) are examined, and so on.
摘要翻译：当搜索关键字提供给内容可寻址存储器（CAM）时，CAM信号指示哪些CAM条目与密钥相匹配。这些信号被提供给权重阵列以选择最高优先级的条目。每个条目的优先级由权重数组中的权重表示。重量阵列处理是流水线的。在流水线阶段0中，检查权重的最高有效位（位0），并且基于最高有效位选择最高优先级。在流水线阶段1，检查下一个最高有效位（位1），依此类推。

5. 发明授权

US06286083B1 Computer system with adaptive memory arbitration scheme 失效
标题翻译：具有自适应内存仲裁方案的计算机系统
公开(公告)号：US06286083B1
公开(公告)日：2001-09-04
申请号：US09112000
申请日：1998-07-08
申请人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
发明人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
摘要翻译：计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。这样的方案可防止低优先级的设备变得“记忆不足”。因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务最迫切的要求。此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

6. 发明授权

US06219709B1 System and method for accessing data files in a computer network 失效
标题翻译：用于访问计算机网络中的数据文件的系统和方法
公开(公告)号：US06219709B1
公开(公告)日：2001-04-17
申请号：US08848713
申请日：1997-05-19
申请人： Derrick John Byford
发明人： Derrick John Byford
IPC分类号： G06F1318
CPC分类号： H04N7/0882 , H04M3/493 , H04M3/4938 , H04M7/006 , H04M7/12
摘要： A system receives a call from a user via a telephone in which the user requests data files from a computer network. A Teletext page is allocated to the user by the system and identified by a number. The system generates a menu in the allocated Teletext page and includes it in a broadcast television signal from which the user makes a selection by pushing a number on the telephone keypad. The number identifies a data file on the computer network. The system writes the information from the requested file to the Teletext page included in the television broadcast signal.
摘要翻译：系统经由用户从计算机网络请求数据文件的电话接收来自用户的呼叫。图文电视页由系统分配给用户，并由号码标识。该系统在所分配的图文电视页面中生成菜单，并将其包括在广播电视信号中，用户通过按电话键盘上的号码进行选择。该号码标识计算机网络上的数据文件。系统将信息从请求的文件写入电视广播信号中包含的图文电视页面。

7. 发明授权

US06189064B1 Graphics display system with unified memory architecture 有权
标题翻译：图形显示系统具有统一的内存架构
公开(公告)号：US06189064B1
公开(公告)日：2001-02-13
申请号：US09437209
申请日：1999-11-09
申请人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
发明人： Alexander G. MacInnis , Chengfuh Jeffrey Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F1318
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。图形显示系统处理模拟视频输入，数字视频输入和图形输入。该系统包含由图形系统，CPU和其他外围设备共享的统一存储器架构。统一存储器架构使用实时调度来服务任务。关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划，同时根据需要为非实时任务进行服务。

8. 发明授权

US06826658B1 Method and apparatus for managing an optical transceiver 有权
标题翻译：用于管理光收发器的方法和装置
公开(公告)号：US06826658B1
公开(公告)日：2004-11-30
申请号：US10177441
申请日：2002-06-20
申请人： Justin L. Gaither , Amjad Odet-Allah
发明人： Justin L. Gaither , Amjad Odet-Allah
IPC分类号： G06F1318
CPC分类号： G06F13/1605 , H04B10/40
摘要： A method and apparatus for managing an optical transceiver includes processing that begins by transceiving management data with modules external to the optical transceiver. The processing then continues by converting the management data transceived with the external modules between a 1st data format (e.g., MDIO interface compatible) and a generic data format (e.g., a format convenient for reading data to and writing data from a random access memory). The processing continues by transceiving management data with modules internal to the optical transceiver. The processing continues by converting the management data transceived with the internal modules between the generic data format and a 2nd data format (e.g., I2C). The processing continues by arbitrating access to a shared memory, which stores the management data in the generic format, between requests from internal modules via the second controller and requests from external modules via the first controller.
摘要翻译：用于管理光收发器的方法和装置包括通过用光收发器外部的模块收发管理数据开始的处理。然后，通过将外部模块收发的管理数据转换为数据格式（例如，与MDIO接口兼容）和通用数据格式（例如，便于将数据从随机读取数据读取和写入数据的格式）访问内存）。通过用光收发器内部的模块收发管理数据，继续处理。通过将通用数据格式和第二个数据格式（例如，I 2 C）之间的内部模块收发的管理数据进行转换，继续处理。通过仲裁对通过第二控制器的来自内部模块的请求之间的通用格式的存储管理数据的共享存储器的访问以及经由第一控制器来自外部模块的请求进行处理。

9. 发明授权

US06784890B1 Accelerated graphics port expedite cycle throttling control mechanism 失效
标题翻译：加速图形端口加快循环调节控制机制
公开(公告)号：US06784890B1
公开(公告)日：2004-08-31
申请号：US09033529
申请日：1998-03-02
申请人： Brian L. Bergeson , Zohar Bogin , Vincent E. VonBokern
发明人： Brian L. Bergeson , Zohar Bogin , Vincent E. VonBokern
IPC分类号： G06F1318
CPC分类号： G06F13/1642
摘要： A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.
摘要翻译：一种用于控制加速循环的方法，其具有确定用于在预定监视窗口期间对组件进行的数据传送请求的时钟周期数量的步骤，并且确保在监视窗口期间处理非加速请求的最小数量的时钟周期。

10. 发明授权

US06510489B2 Memory interface circuit 失效
公开(公告)号：US06510489B2
公开(公告)日：2003-01-21
申请号：US10043236
申请日：2002-01-14
申请人： Eiji Komoto
发明人： Eiji Komoto
IPC分类号： G06F1318
CPC分类号： G06F13/18 , G11C11/406
摘要： A memory bus arbitrating circuit selects the request signal with the highest priority when a plurality of types of same are inputted simultaneously. A memory controlling circuit executes relative to memory control of memory bus arbitrating circuit-selected processing. A first monitoring circuit outputs a first refresh request signal when the count value of a refresh counter reaches a first prescribed value. A second monitoring circuit outputs a second refresh request signal when the count value of a refresh counter reaches a second prescribed value, which is, for example, ½ of the first prescribed value. The first, second refresh request signals are inputted to the memory bus arbitrating circuit. The memory bus arbitrating circuit regards the first refresh request signal as the request signal with the highest priority, and regards the second refresh request signal as the request signal with the lowest priority. When the second refresh request signal is inputted, memory refresh is performed only when there are no other processing requests, and when the first refresh request signal is inputted, memory refresh is performed in a compulsory manner even if there is other processing. After refresh, the count value of the refresh counter is reset. By using a second refresh request signal, it is possible to reduce the probability of the first refresh request signal being inputted to the memory bus arbitrating circuit at the same time as a request signal of other processing.

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