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1. 发明授权

US06880069B1 Replay instruction morphing 失效
公开(公告)号：US06880069B1
公开(公告)日：2005-04-12
申请号：US09608567
申请日：2000-06-30
申请人： Douglas M. Carmean , David J. Sager , Thomas F. Toll , Karol F. Menezes
发明人： Douglas M. Carmean , David J. Sager , Thomas F. Toll , Karol F. Menezes
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.

2. 发明授权

US08347066B2 Replay instruction morphing 有权
标题翻译：重播指示变形
公开(公告)号：US08347066B2
公开(公告)日：2013-01-01
申请号：US11069004
申请日：2005-02-28
申请人： Douglas M. Carmean , David J. Sager , Thomas F. Toll , Karol F. Menezes
发明人： Douglas M. Carmean , David J. Sager , Thomas F. Toll , Karol F. Menezes
IPC分类号： G06F9/38
CPC分类号： G06F9/3861
摘要： Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.
摘要翻译：重播指示变形。所公开的装置包括执行指令的执行单元。如果执行单元错误地执行指令，则重放系统重放改变的指令。

3. 发明授权

US06981129B1 Breaking replay dependency loops in a processor using a rescheduled replay queue 失效
标题翻译：使用重新安排的重播队列在处理器中重新播放依赖循环
公开(公告)号：US06981129B1
公开(公告)日：2005-12-27
申请号：US09705668
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重新安排的重播队列在处理器中重新播放依赖循环。所述处理器包括用于接收多个指令的重放队列，以及执行所述多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。检查器耦合到执行单元以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

4. 发明授权

US06877086B1 Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter 失效
标题翻译：使用重放队列和计数器在处理器中重新安排多个微操作的方法和装置
公开(公告)号：US06877086B1
公开(公告)日：2005-04-05
申请号：US09705678
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重放队列在处理器中重新安排多个微操作。处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地安排执行指令并将每个指令分派到执行单元。检查器耦合到执行单元以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

5. 发明申请

US20140281424A1 TRACKING CONTROL FLOW OF INSTRUCTIONS 有权
标题翻译：跟踪指令的控制流程
公开(公告)号：US20140281424A1
公开(公告)日：2014-09-18
申请号：US13834049
申请日：2013-03-15
申请人： Jayaram Bobba , Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Arvind Krishnaswamy , David J. Sager , Jason M. Agron
发明人： Jayaram Bobba , Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Arvind Krishnaswamy , David J. Sager , Jason M. Agron
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F8/433 , G06F11/0715 , G06F11/0721 , G06F11/076 , G06F11/3466
摘要： A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.
摘要翻译：公开了一种用于跟踪应用程序中的指令的控制流程并基于应用程序中的指令的控制流程执行处理设备的一个或多个优化的机制。生成控制流数据以指示应用程序中的指令块的控制流程。控制流数据可以包括指示是否可以针对不同的指令块执行优化的注释。控制流数据还可以用于跟踪指令的执行以确定指令块中的指令是否被分配给处理器的线程，进程和/或执行核心，并且确定错误是否具有在执行指令期间发生。

6. 发明申请

US20110167416A1 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 有权
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：US20110167416A1
公开(公告)日：2011-07-07
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

7. 发明申请

US20090327661A1 MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS 审中-公开
标题翻译：用于SMT订单处理器的免费物理寄存器识别器的机制
公开(公告)号：US20090327661A1
公开(公告)日：2009-12-31
申请号：US12165186
申请日：2008-06-30
申请人： Zeev Sperber , David J. Sager , Fernando Latorre , Ori Lempel , Evgeni Krimer , Bishara Shomar
发明人： Zeev Sperber , David J. Sager , Fernando Latorre , Ori Lempel , Evgeni Krimer , Bishara Shomar
IPC分类号： G06F9/305
CPC分类号： G06F9/3851 , G06F9/30098 , G06F9/384 , G06F9/3885
摘要： Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed.
摘要翻译：描述了用于处理SMT（同时多线程）无序处理器的免费物理寄存器标识符的机制的方法和装置。在一些实施例中，物理寄存器文件存储对应于多个寄存器的推测数据和架构数据。空闲列表逻辑可以保持与多个寄存器对应的空闲物理寄存器标识符。指令可以在调度时从物理寄存器文件读取架构数据。还描述和要求保护其他实施例。

8. 发明授权

US07219349B2 Multi-threading techniques for a processor utilizing a replay queue 有权
标题翻译：使用重放队列的处理器的多线程技术
公开(公告)号：US07219349B2
公开(公告)日：2007-05-15
申请号：US10792154
申请日：2004-03-02
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/46 , G06F9/40 , G06F15/76
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

9. 发明授权

US06792446B2 Storing of instructions relating to a stalled thread 有权
标题翻译：存储与停止的线程相关的指令
公开(公告)号：US06792446B2
公开(公告)日：2004-09-14
申请号：US10060264
申请日：2002-02-01
申请人： Amit A. Merchant , Darrell D. Buggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Buggs , David J. Sager
IPC分类号： G06F900
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

10. 发明授权

US06172933B2 Redundant form address decoder for memory system 有权
标题翻译：用于存储系统的冗余表格地址解码器
公开(公告)号：US06172933B2
公开(公告)日：2001-01-09
申请号：US09148314
申请日：1998-09-04
申请人： David J. Sager
发明人： David J. Sager
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： The present invention provides a memory system that retrieves data based upon redundant form address data. The memory system includes a memory having a plurality of memory lines and an address decoder that enables one of the memory lines in response to a redundant form address signal. A redundant form decoder decodes redundant form data into a differential pair of decoded address lines for each bit position of a memory address. One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line by memory line basis, using the address of the memory lines themselves. The redundant form address decoder avoids a completion add that would otherwise be required, yielding very fast access to memory.
摘要翻译：本发明提供了一种基于冗余形式地址数据检索数据的存储系统。存储器系统包括具有多个存储器线的存储器和地址解码器，其能够响应于冗余形式地址信号使存储器线路之一响应。冗余形式解码器将冗余形式数据解码为存储器地址的每个位位置的解码地址线的差分对。两个差分对之一承载正确的地址数据。要使用的一条地址线使用存储器线本身的地址在存储器线的基础上由存储器线确定。冗余形式地址解码器避免了否则将需要的完成添加，从而非常快速地访问存储器。

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