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1. 发明授权

US06981129B1 Breaking replay dependency loops in a processor using a rescheduled replay queue 失效
标题翻译：使用重新安排的重播队列在处理器中重新播放依赖循环
公开(公告)号：US06981129B1
公开(公告)日：2005-12-27
申请号：US09705668
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprises a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重新安排的重播队列在处理器中重新播放依赖循环。所述处理器包括用于接收多个指令的重放队列，以及执行所述多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。检查器耦合到执行单元以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

2. 发明授权

US06877086B1 Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter 失效
标题翻译：使用重放队列和计数器在处理器中重新安排多个微操作的方法和装置
公开(公告)号：US06877086B1
公开(公告)日：2005-04-05
申请号：US09705678
申请日：2000-11-02
申请人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
发明人： Darrell D. Boggs , Douglas M. Carmean , Per H. Hammarlund , Francis X. McKeen , David J. Sager , Ronak Singhal
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
摘要翻译：使用重放队列在处理器中重新安排多个微操作。处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。调度器耦合在重播队列和执行单元之间。调度器推测性地安排执行指令并将每个指令分派到执行单元。检查器耦合到执行单元以确定每个指令是否已成功执行。检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

3. 发明授权

US07797683B2 Decoupling the number of logical threads from the number of simultaneous physical threads in a processor 有权
标题翻译：从处理器中同时处理的物理线程的数量解耦逻辑线程数
公开(公告)号：US07797683B2
公开(公告)日：2010-09-14
申请号：US10745527
申请日：2003-12-29
申请人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
发明人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
IPC分类号： G06F9/44
CPC分类号： G06F9/485 , G06F9/3851
摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.
摘要翻译：管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。

4. 发明授权

US06643747B2 Processing requests to efficiently access a limited bandwidth storage area 有权
公开(公告)号：US06643747B2
公开(公告)日：2003-11-04
申请号：US09751625
申请日：2000-12-27
申请人： Per H. Hammarlund , Douglas M. Carmean , Michael D. Upton
发明人： Per H. Hammarlund , Douglas M. Carmean , Michael D. Upton
IPC分类号： G06F1200
CPC分类号： G06F12/0857
摘要： A request received from a requester to access a processor cache or register file or the like is buffered, by storing requestor identification, request type, address, and a status of the request. This buffered request may be forwarded to the cache if it has the highest priority among a number of buffered requests that also wish to access the cache. The priority is a function of at least the requestor identification, the requester type, and the status of the request. For buffered requests which include a read, the buffered request is deleted after, not before, receiving an indication that the requestor has received the data read from the cache.

5. 发明授权

US07640419B2 Method for and a trailing store buffer for use in memory renaming 失效
标题翻译：用于存储器重命名的方法和后端存储缓冲区
公开(公告)号：US07640419B2
公开(公告)日：2009-12-29
申请号：US10743422
申请日：2003-12-23
申请人： Sebastien Hily , Per H. Hammarlund
发明人： Sebastien Hily , Per H. Hammarlund
IPC分类号： G06F9/30
CPC分类号： G06F9/3834
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient memory renaming. The method includes computing a store address, writing the store address in a first storage, writing data associated with the store address to a memory, and de-allocating the store address from the first storage, allocating the store address in a second storage, predicting a load instruction to be memory renamed, computing a load store source index, computing a load address, disambiguating the memory renamed load instruction, and retiring the memory renamed load instruction, if the store instruction is still allocated in at least one of the first storage and the second storage and should have effectively provided to the load the full data. The method may also include re-executing the load instruction without memory renaming, if the store instruction is not in at the first storage or in the second storage.
摘要翻译：本发明的实施例涉及一种能够实现高效存储器重命名的存储器管理方案和装置。该方法包括计算存储地址，将存储地址写入第一存储器中，将与存储地址相关联的数据写入存储器，以及从第一存储器解除存储地址，在第二存储器中分配存储地址，预测存储地址如果所述存储指令仍被分配在所述第一存储器中的至少一个中，则存储指令被重新命名为存储器重命名的加载指令，计算加载存储源索引，计算加载地址，消除所述存储器重命名的加载指令，以及退出所述存储器重命名加载指令，并且第二个存储应该有效地提供给负载的完整数据。如果存储指令不在第一存储器或第二存储器中，则该方法还可以包括重新执行加载指令而不进行存储器重命名。

6. 发明授权

US07529913B2 Late allocation of registers 失效
标题翻译：寄存器后期分配
公开(公告)号：US07529913B2
公开(公告)日：2009-05-05
申请号：US10743065
申请日：2003-12-23
申请人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
发明人： Avinash Sodani , Per H. Hammarlund , Stephan J. Jourdan
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30098 , G06F9/30181 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers during operations in a pipeline of the processor.
摘要翻译：本发明的实施例涉及一种用于提供与计算机处理器中的物理寄存器相对应的虚拟标识符的方法和系统。根据实施例，虚拟标识符可以用于在处理器的流水线中的操作期间表示物理寄存器。

7. 发明授权

US06105111A Method and apparatus for providing a cache management technique 失效
标题翻译：用于提供高速缓存管理技术的方法和装置
公开(公告)号：US06105111A
公开(公告)日：2000-08-15
申请号：US53527
申请日：1998-03-31
申请人： Per H. Hammarlund , Glenn J. Hinton
发明人： Per H. Hammarlund , Glenn J. Hinton
IPC分类号： G06F12/12 , G06F12/00
CPC分类号： G06F12/123
摘要： A cache technique for maximizing cache efficiency by assigning ages to elements which access the cache, is described. In one embodiment, the cache technique includes receiving a first element of a first type by a cache and writing the first element in a set of the cache. The first element has a first age. The cache technique further includes receiving a second element of a second type by the cache and writing the second element in the set of the cache. The second element has a middle age, where the first age is a more recently used age than the middle age. In another embodiment, the cache technique includes receiving a first element of a first stream by a cache and writing the first element in a set of the cache. The first element has a first age. The cache technique further includes receiving a second element of a second stream by the cache and writing the second element in the set of the cache. The second element has a middle age, where the first age is a more recently used age than the middle age.
摘要翻译：描述了通过将访问高速缓存的元素分配年龄来最大化高速缓存效率的高速缓存技术。在一个实施例中，高速缓存技术包括通过高速缓存接收第一类型的第一元素并将第一元素写入高速缓存的集合。第一个元素有第一个年龄。高速缓存技术还包括由高速缓存接收第二类型的第二元素，并将第二元素写入高速缓存的集合。第二个元素有一个中年，第一个年龄是比中年更近的年龄。在另一个实施例中，高速缓存技术包括由高速缓存接收第一流的第一元素，并将第一元素写入高速缓存的集合。第一个元素有第一个年龄。高速缓存技术还包括由高速缓存接收第二流的第二元素，并将第二元素写入高速缓存的集合。第二个元素有一个中年，第一个年龄是比中年更近的年龄。

8. 发明授权

US07688746B2 Method and system for dynamic resource allocation 失效
标题翻译：动态资源分配的方法和系统
公开(公告)号：US07688746B2
公开(公告)日：2010-03-30
申请号：US10745701
申请日：2003-12-29
申请人： Per H. Hammarlund , Melih Ozgul
发明人： Per H. Hammarlund , Melih Ozgul
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
CPC分类号： G06F9/5011 , Y02D10/22
摘要： Embodiments of the present invention provide a dynamic resource allocator to allocate resources performance optimization in, for example, a computer system. The dynamic resource allocator to allocate a resource to one or more threads associated with an application based on a performance rate. Embodiments of the present invention may further include a performance monitor to monitor the performance rate of the one or more threads. The dynamic resource allocator to allocate an additional resource to the one or more threads, if the thread is performing above a performance threshold. In embodiments of the present invention, the dynamic resource allocation strategy may be decided based on, for example, optimizing the overall system throughput, minimizing power consumption, meeting system performance goals (e.g., real time requirements), user specified performance priorities and/or application specified performance priorities.
摘要翻译：本发明的实施例提供了一种动态资源分配器，用于在例如计算机系统中分配资源性能优化。动态资源分配器，用于基于性能速率向与应用程序相关联的一个或多个线程分配资源。本发明的实施例还可以包括监视一个或多个线程的性能速率的性能监视器。如果线程在性能阈值以上执行，动态资源分配器将向一个或多个线程分配附加资源。在本发明的实施例中，动态资源分配策略可以基于例如优化整个系统吞吐量，最小化功耗，满足系统性能目标（例如，实时要求），用户指定的性能优先级和/或应用指定的性能优先级。

9. 发明授权

US06990551B2 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache 失效
公开(公告)号：US06990551B2
公开(公告)日：2006-01-24
申请号：US10917449
申请日：2004-08-13
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Per H. Hammarlund
IPC分类号： G06F12/08
CPC分类号： G06F12/1054 , G06F12/1063 , G06F12/109
摘要： A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.

10. 发明授权

US06560690B2 System and method for employing a global bit for page sharing in a linear-addressed cache 有权
公开(公告)号：US06560690B2
公开(公告)日：2003-05-06
申请号：US09753330
申请日：2000-12-29
申请人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
发明人： Herbert H. J. Hum , Stephan J. Jourdan , Deborrah Marr , Per H. Hammarlund
IPC分类号： G06F1200
CPC分类号： G06F12/1063 , G06F2212/656
摘要： A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address does not reside in the global/non-global linear-addressed cache memory, then a cache line selected by a replacement policy has its data block replaced with a data block from a storage device at a higher hierarchical level as specified by the linear address.

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