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1. 发明授权

US06403426B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06403426B1
公开(公告)日：2002-06-11
申请号：US09527202
申请日：2000-03-16
申请人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
发明人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1045 , H01L29/66537 , H01L29/66545 , H01L29/6659
摘要： In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region 4 of a first conductivity type is defined at the surface 2 of the semiconductor body 1, and a patterned layer is applied consisting of refractory material, which patterned layer defines the area of the planned gate to be provided at a later stage of the process and acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. In a next step, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess 15 in the dielectric layer 14 at the area of the planned gate. Then, impurities are introduced via the recess 15 into the channel region 13 of the semiconductor body 1 in a self-registered way by using the dielectric layer 14, as a mask and an insulating layer is applied, forming the gate dielectric, on which insulating layer a conductive layer is applied thereby filling the recess, which conductive layer is shaped into the gate of the transistor.
摘要翻译：在制造半导体器件的方法中，该半导体器件包括晶体管，该晶体管具有通过栅极电介质在半导体本体的表面处与沟道区绝缘的栅极，在半导体本体的表面2处限定第一导电类型的有源区域4 1，并且施加由耐火材料组成的图案层，该图案层限定了将在该工艺的稍后阶段提供的规划浇口的区域，并且在形成源区11和排水区期间用作掩模在下一步骤中，提供电介质层14，其厚度足够大以覆盖图案化层，该电介质层14通过部分厚度被去除其厚度的一部分，借助于直到图案化层被暴露之前的材料去除处理，去除图案层，从而在计划的栅极的区域处在电介质层14中形成凹陷15。然后，通过使用电介质层14作为掩模，并且施加绝缘层，通过凹部15将杂质以自我注册的方式引入半导体本体1的沟道区域13中，形成栅极电介质，绝缘施加导电层，从而填充凹部，该导电层被成形为晶体管的栅极。

2. 发明授权

US06251729B1 Method of manufacturing a nonvolatile memory 有权
标题翻译：制造非易失性存储器的方法
公开(公告)号：US06251729B1
公开(公告)日：2001-06-26
申请号：US09464004
申请日：1999-12-15
申请人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
发明人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11539 , H01L29/66545
摘要： In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type. In a next step, a dielectric layer is applied, which is removed over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region and is exposed, after which the silicon-containing first active region are removed, thereby forming a recess in the dielectric layer. Subsequently, a second insulating layer is applied at the second active region providing an inter-gate dielectric of the memory element, and a third insulating layer is applied at the first active region providing a gate dielectric of the transistor. After formation of the gate dielectric and the inter-gate dielectric, a conductive layer is applied which is shaped into a gate of the transistor at the first active region and a control gate of the memory element at the second active region.
摘要翻译：在半导体本体的表面上制造包括场效晶体管和非易失性存储元件的半导体器件的方法中，第一导电类型的第一和第二有源区限定在半导体本体的表面分别用于晶体管和存储器元件。半导体本体的表面随后涂覆有提供晶体管的牺牲栅极电介质和存储元件的浮置栅极电介质的第一绝缘层，该第一绝缘层然后被含硅层覆盖，所述含硅层提供牺牲栅极晶体管和存储元件的浮动栅极。在形成牺牲栅极和浮置栅极之后，晶体管和存储元件设置有第二导电类型的源区和漏区。在下一步骤中，施加电介质层，其通过材料去除处理至少部分其厚度去除，直到在第一和第二有源区域处的含硅层被暴露，然后将硅除去第一有源区，从而在电介质层中形成凹部。随后，在第二有源区施加第二绝缘层，提供存储元件的栅极间电介质，并且在提供晶体管的栅极电介质的第一有源区施加第三绝缘层。在形成栅极电介质和栅极间电介质之后，施加导电层，该导电层在第一有源区域被成形为晶体管的栅极，并且在第二有源区域处形成存储元件的控制栅极。

3. 发明授权

US06177303B1 Method of manufacturing a semiconductor device with a field effect transistor 有权
标题翻译：制造具有场效应晶体管的半导体器件的方法
公开(公告)号：US06177303B1
公开(公告)日：2001-01-23
申请号：US09379959
申请日：1999-08-24
申请人： Jurriaan Schmitz , Pierre H. Woerlee , Andreas H. Montree
发明人： Jurriaan Schmitz , Pierre H. Woerlee , Andreas H. Montree
IPC分类号： H01L21337
CPC分类号： H01L29/6659 , H01L21/28079 , H01L29/495 , H01L29/66545
摘要： In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (4) and a nitride layer (5) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (10).
摘要翻译：在已知的替代栅极工艺中，通过沉积厚的氧化物层，然后通过CMP平坦化该层，直到达到栅极，该相对高欧姆的多晶硅栅极被低欧姆金属栅极代替，该栅极可被选择性地去除和替换由金属门。通过将栅极结构设置为多晶硅栅极顶部的虚设多晶硅栅极（4）和氮化物层（5）的叠层，可大大简化工艺。当在CMP期间达到氮化物层时，停止CMP，从而排除对聚合物的攻击。相对于氧化物层（10）选择性地去除氮化物和多晶硅。

4. 发明授权

US06368915B1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06368915B1
公开(公告)日：2002-04-09
申请号：US09527203
申请日：2000-03-16
申请人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
发明人： Andreas H. Montree , Jurriaan Schmitz , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/66825
摘要： In a method of manufacturing a semiconductor device comprising a non-volatile memory element, an active region 4 of a first conductivity type is defined at a surface 2 of a semiconductor body 1, and a patterned layer is applied, which patterned layer acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. Then, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer 14. In this recess a first insulating layer is applied providing a floating gate dielectric 19, to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer 14, which first conductive layer is shaped into a floating gate 21 by means of masked etching. The floating gate 21 has a substantially flat surface portion 22 extending substantially parallel to the surface 2 of the semiconductor body 1 and sidewall portions 23 extending substantially perpendicularly to the surface 2 of the semiconductor body 1. In a next step, the floating gate 21 is covered with a second insulating layer providing an inter-gate dielectric 25, to which second insulating layer a second conductive layer is applied, which is shaped into an overlapping control gate 27. The control gate 27 is capacitively coupled to the substantially flat surface portion 22 of the floating gate 21 and to at least the sidewall portions 23 of the floating gate 21 situated adjacent to the source zone 11 and the drain zone 12 of the memory element.
摘要翻译：在制造包括非易失性存储元件的半导体器件的方法中，第一导电类型的有源区4限定在半导体本体1的表面2，并且施加图案化层，该图案层用作在半导体本体1中形成第二导电类型的源极区11和漏极区12期间形成掩模。然后，提供足够大以覆盖图案化层的厚度的电介质层14，该电介质层14 通过材料去除处理去除其厚度的一部分，直到图案化层被暴露，去除图案层，从而在电介质层14中形成凹陷。在该凹槽中，施加第一绝缘层，提供浮动栅极电介质19，第一绝缘层施加第一导电层，填充介电层14中的凹部，该第一导电层被成形为浮动栅极21 通过掩模蚀刻。浮动栅极21具有基本上平行于半导体本体1的表面2延伸的基本上平坦的表面部分22，以及基本上垂直于半导体本体1的表面2延伸的侧壁部分23.在下一步骤中，浮动栅极21是覆盖有提供栅极间电介质25的第二绝缘层，施加第二绝缘层的第二导电层被成形为重叠的控制栅极27.控制栅极27电容耦合到基本平坦的表面部分22 和至少位于与存储元件的源极区11和漏极区12相邻的浮动栅极21的侧壁部分23。

5. 发明授权

US06255183B1 Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers 失效
标题翻译：具有使用SiGe间隔物的具有LDD结构的MOS晶体管的半导体器件的制造
公开(公告)号：US06255183B1
公开(公告)日：2001-07-03
申请号：US09064207
申请日：1998-04-22
申请人： Jurriaan Schmitz , Youri V. Ponomarev , Pierre H. Woerlee
发明人： Jurriaan Schmitz , Youri V. Ponomarev , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/28247 , H01L21/823864 , H01L29/665 , Y10S438/923
摘要： A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implated, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed. In the method, a layer of semiconductor material formed by Si1-xGex, 0.1
摘要翻译：一种制造具有LDD结构的MOS晶体管的半导体器件的方法。在硅衬底（1）的表面（5）上形成栅电介质（6）和栅电极（7,8）。然后暴露与栅电极相邻的表面，并且在与栅电极相邻的表面的边缘（9）上形成一层半导体材料（10）。随后，栅极电极和半导体材料层用作掩模，随后引入离子（13,14）。最后，进行热处理，由此通过激活注入的离子并且通过从半导体材料层扩散掺杂剂的原子而形成源极区（16,17）和漏极区（18,19）。这些由扩散形成的这些区域的部分（b）在这里是弱掺杂的，位于通过激活注入的离子和沟道区（20,21）形成的更强的掺杂部分（a）之间。因此形成了LDD结构。在该方法中，在与栅电极相邻的边缘上设置由Si1-xGex形成的半导体材料层，0.1

6. 发明授权

US06476430B1 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US06476430B1
公开(公告)日：2002-11-05
申请号：US09656990
申请日：2000-09-07
申请人： Jurriaan Schmitz , Andreas H. Montree
发明人： Jurriaan Schmitz , Andreas H. Montree
IPC分类号： H01L2980
CPC分类号： H01L27/088 , H01L21/823418
摘要： In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD implantation. The halo implant, however, decreases the analog performance of transistors. To combine suppression of short-channel effects with a high analog performance, it is proposed to provide only transistors T1, which are not intended for analog functions with the halo implant (16), and to mask the analog transistors T2 with a mask (15) against the halo implant. To avoid short-channel effects in T2, this transistor is provided with a channel whose length is larger than that of transistor T1.
摘要翻译：在具有亚微米通道的晶体管中，通常通过在源极/漏极区域中的晕（或凹穴）注入来抑制诸如阈值电压降低的短沟道效应，该操作与LDD 植入。然而，光晕注入降低了晶体管的模拟性能。为了组合抑制短信道效应和高模拟性能，建议仅提供不用于具有光晕注入（16）的模拟功能的晶体管T1，并且用掩模（15）屏蔽模拟晶体管T2 ）抵抗晕植入物。为了避免T2中的短沟道效应，该晶体管具有长度大于晶体管T1的沟道。

7. 发明授权

US07262460B2 Vertical insulated gate transistor and manufacturing method 有权
标题翻译：垂直绝缘栅晶体管及其制造方法
公开(公告)号：US07262460B2
公开(公告)日：2007-08-28
申请号：US10538216
申请日：2003-12-08
申请人： Jurriaan Schmitz , Raymond J. E. Hueting , Erwin A. Hijzen , Andreas H. Montree , Michael A. A. In't Zandt , Gerrit E. J. Koops
发明人： Jurriaan Schmitz , Raymond J. E. Hueting , Erwin A. Hijzen , Andreas H. Montree , Michael A. A. In't Zandt , Gerrit E. J. Koops
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

8. 发明授权

US06271551B1 Si-Ge CMOS semiconductor device 失效
标题翻译： Si-Ge CMOS半导体器件
公开(公告)号：US06271551B1
公开(公告)日：2001-08-07
申请号：US08764914
申请日：1996-12-13
申请人： Jurriaan Schmitz , Pierre H. Woerlee
发明人： Jurriaan Schmitz , Pierre H. Woerlee
IPC分类号： H01L2976
CPC分类号： H01L29/66477 , H01L21/823807 , H01L29/1054 , H01L29/1079 , H01L29/1083
摘要： To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surface region, a few tens of nm below the surface. It was found, however, that degradation of the mobility can occur particularly in n-channel transistors owing to diffusion of boron atoms from the strongly doped layer to the surface, for example during the formation of the gate oxide. To prevent this degradation, a thin layer 11 of Si1−xGex inhibiting boron diffusion is provided between the strongly doped layer 10 and the intrinsic surface region 7, for example with x=0.3. The SiGe layer and the intrinsic surface region may be provided epitaxially, the thickness of the SiGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate 1 in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained. Since SiGe has a diffusion-accelerating rather than decelerating effect on n-type dopants, the ground plane of a p-channel transistor in a CMOS embodiment is doped with As or Sb because of the low diffusion rate of these elements in pure silicon.
摘要翻译：为了在具有深亚微米范围的沟道尺寸的MOS晶体管中获得高迁移率和合适的阈值电压，期望在弱掺杂的本征表面区域下面的沟道区域中埋设强掺杂层（或接地平面）在表面下方几十nm。然而，已经发现，由于硼原子从强掺杂层扩散到表面，例如在形成栅极氧化物期间，特别是在n沟道晶体管中可能发生迁移率的降低。为了防止这种劣化，例如在x = 0.3处，在强掺杂层10和固有表面区域7之间设置抑制硼扩散的Si1-xGex薄层11。可以外延地提供SiGe层和本征表面区域，SiGe层的厚度如此之小，使得外延层中的晶格常数与平行于表面的平面中的衬底1中的晶格常数没有或基本上没有不同，同时保留足够的扩散抑制作用。由于SiGe对n型掺杂剂具有扩散加速而不是减速效应，所以CMOS实施例中的p沟道晶体管的接地面由于在纯硅中这些元素的低扩散速率掺杂有As或Sb。

9. 发明授权

US06303453B1 Method of manufacturing a semiconductor device comprising a MOS transistor 有权
标题翻译：制造包括MOS晶体管的半导体器件的方法
公开(公告)号：US06303453B1
公开(公告)日：2001-10-16
申请号：US09329030
申请日：1999-06-09
申请人： Jurriaan Schmitz , Pierre H. Woerlee
发明人： Jurriaan Schmitz , Pierre H. Woerlee
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/2255 , H01L21/31155
摘要： The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (IA) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2). In a method according to the invention, the LDD regions (3A, 4A) are made as follows: in a first step, suitable doping atoms (D) are implanted into the dielectric layer (1B), in a second ion implantation (I2), and subsequently in a second step, a part of the doping atoms (D) is diffused from the dielectric layer (1B) into the silicon substrate (10, 11), whereby the LDD regions (3A, 4A) are formed. This method enables a MOST with excellent properties to be obtained, for example with a flatter profile of the threshold voltage versus the gate-electrode (2) length (curve 130) than in conventionally made MOSTs (curve 131). This result is obtained in a simple and reproducible manner.
摘要翻译：本发明涉及制造（水平）MOST的方法，例如在（BI）CMOS IC中使用的MOST。在栅电极（2）的任一侧上，位于栅极氧化物（IA）上方的硅衬底（10,11）的表面在源（3）的位置处设置有电介质层（1B）并形成漏极（4），该介质层包括形成为起始层的热氧化物层（1B）。源极（3）和/或漏极（4）设置有LDD区域（3A，4A），源极（3）和漏极（4）的其余部分（3B，4B）由离子注入（I1）掺杂到硅衬底（10,11）中。以这种方式获得的MOST仍然遭受所谓的短沟道效应，导致阈值电压对栅电极（2）的长度的实质依赖性，特别是在非常短的栅电极长度的情况下（2）。在根据本发明的方法中，LDD区域（3A，4A）如下制造：在第一步骤中，在第二离子注入（I2）中，将合适的掺杂原子（D）注入介电层（1B），随后在第二步骤中，掺杂原子（D）的一部分从电介质层（1B）扩散到硅衬底（10,11）中，由此形成LDD区域（3A，4A）。该方法使得能够获得具有优异性能的MOST，例如与常规制作的MOST（曲线131）相比，阈值电压相对于栅电极（2）长度（曲线130）的平坦轮廓。该结果以简单且可再现的方式获得。

10. 发明申请

US20050029572A1 Fabrication of non-volatile memory cell 审中-公开
标题翻译：非易失性存储单元的制造
公开(公告)号：US20050029572A1
公开(公告)日：2005-02-10
申请号：US10499395
申请日：2002-12-20
申请人： Jurriaan Schmitz
发明人： Jurriaan Schmitz
IPC分类号： H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114
摘要： Fabrication of a semiconductor device comprising a compact cellon a semiconductor substrate (3) including at least two adjacent elements separated by a spacing, the elements being defined from a layer stack that includes an isolation layer(4) on the substrate (3) and a poly-Si layer (5) on the isolation layer (4), wherein the fabrication includes:—depositing on the layer stack a mask (M1; M3) including at least one vertical isolation layer (10), a first (9) and a second (11) silicon nitride layer, the vertical isolation layer (10) separating the first (9) and second (11) silicon nitride layers and being located where the spacing is to be formed;—performing a first selective etch on the vertical isolation layer (10) to form a narrow slit (A);—performing a stack etch including a first stack etch process for selectively etching the poly-Si layer (5), using thenarrow slit (A) to define the location for the first stack etch process and the spacing between the elements.
摘要翻译：包括紧密蜂窝半导体器件的半导体器件的制造，所述半导体衬底（3）包括由间隔隔开的至少两个相邻元件，所述元件由层叠体限定，所述层叠层包括在所述衬底（3）上的隔离层（4）在所述隔离层（4）上的多晶硅层（5），其中所述制造包括： - 在所述层堆叠上沉积包括至少一个垂直隔离层（10），第一（9）和第二（11）氮化硅层，所述垂直隔离层（10）分离所述第一（9）和第二（11）氮化硅层，并且位于要形成间隔的位置; - 在垂直方向上执行第一选择性蚀刻隔离层（10）以形成窄缝（A）; - 执行堆叠蚀刻，其包括用于选择性地蚀刻所述多晶硅层（5）的第一堆叠蚀刻工艺，使用所述狭缝（A）来限定所述第一堆栈蚀刻过程和元素之间的间距。

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