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1. 发明授权

US5502326A Semiconductor device provided having a programmable element with a high-conductivity buried contact region 失效
标题翻译：提供具有可编程元件的半导体器件具有高导电性掩埋接触区域
公开(公告)号：US5502326A
公开(公告)日：1996-03-26
申请号：US381002
申请日：1995-01-25
申请人： Jan W. Slotboom , Pierre H. Woerlee , Reinout Woltjer
发明人： Jan W. Slotboom , Pierre H. Woerlee , Reinout Woltjer
IPC分类号： H01L27/10 , G11C17/16 , H01L21/8246 , H01L23/525 , H01L27/102 , H01L27/112 , H01L29/00 , H01L27/095
CPC分类号： G11C17/16 , H01L23/5252 , H01L2924/0002 , Y10S257/91
摘要： A semiconductor device includes a programmable element having a doped semiconductor region (4) and a conductor region (6) which are separated from one another by at least a portion of an insulating layer (5). The conductor region (6) is of a material suitable for forming a rectifying junction (8) with the material of the semiconductor region (4). To achieve a comparatively high conductivity connection to the semiconductor region (4), the element is further provided with a contact region (3) which has a comparatively low electrical resistance compared with the semiconductor region (4). The contact region (3) is provided at a side of the semiconductor region (4) remote from the insulating layer (5) and is separated from the insulating layer (5) by the semiconductor region (4). Both the semiconductor region (4) and the contact region (5) are laterally bounded by an isolating region (7) at opposing sides. The invention thus offers a device provided with a programmable element of a substantially more compact structure than a comparable conventional programmable element.
摘要翻译：半导体器件包括具有掺杂半导体区域（4）的可编程元件和通过绝缘层（5）的至少一部分彼此分离的导体区域（6）。导体区域（6）是适于与半导体区域（4）的材料形成整流结（8）的材料。为了实现与半导体区域（4）的较高的导电性连接，元件还具有与半导体区域（4）相比具有相对低的电阻的接触区域（3）。接触区域（3）设置在远离绝缘层（5）的半导体区域（4）的一侧，并且通过半导体区域（4）与绝缘层（5）分离。半导体区域（4）和接触区域（5）都由相对侧的隔离区域（7）横向界定。因此，本发明提供了一种具有比可比较的常规可编程元件基本上更紧凑结构的可编程元件的装置。

2. 发明授权

US5416343A Semiconductor device provided with a number of programmable elements 失效
标题翻译：具有多个可编程元件的半导体器件
公开(公告)号：US5416343A
公开(公告)日：1995-05-16
申请号：US306854
申请日：1994-09-15
申请人： Jan W. Slotboom , Pierre H. Woerlee , Reinout Woltjer
发明人： Jan W. Slotboom , Pierre H. Woerlee , Reinout Woltjer
IPC分类号： G11C17/16 , H01L23/525 , H01L27/10 , G11C17/00 , H01L27/04
CPC分类号： G11C17/16 , H01L23/5252 , H01L2924/0002 , Y10S257/91
摘要： A semiconductor device includes a number of programmable elements arranged in a matrix of rows and columns. The elements each have a doped semiconductor region (10) and a conductor region (20) which are mutually separated by an insulating layer (8). The conductor region (20) can be a material suitable for forming a rectifying junction (35) with the material of the semiconductor region (10). Within a row, the conductor regions of the programmable elements present therein are coupled to a common row conductor (21 . . . 23), and within a column the semiconductor regions of the programmable elements situated therein are connected to a common column conductor (11 . . . 14). To program an element, a programming voltage V.sub.PROG can be applied between the column and row conductors associated with the element to be programmed during operation, which voltage is greater than the breakdown voltage of at least a portion of the insulating layer (8) situated between the semiconductor region (10) and the conductor region (20) of the element. The programming voltage is applied with such a polarity that majority charge carriers in the semiconductor region (10) are drawn to an interface (4) between the semiconductor region (10) and the insulating layer (8), forming an accumulation layer (31) there. Between the remaining column and row conductors, on the other hand, the programming voltage is offered with an opposite polarity. Thus the programming of the matrix can take place, if so desired, by means of only a single voltage level V.sub.PROG.
摘要翻译：半导体器件包括以行和列的矩阵排列的多个可编程元件。这些元件各自具有由绝缘层（8）相互分离的掺杂半导体区域（10）和导体区域（20）。导体区域（20）可以是适于与半导体区域（10）的材料形成整流结（35）的材料。在一行内，其中存在的可编程元件的导体区域耦合到公共行导体（21 ... 23），并且在列内，位于其中的可编程元件的半导体区域连接到公共列导体（11 ... 14）。为了对元件进行编程，编程电压VPROG可以施加在与要在操作期间被编程的元件相关联的列和行导体之间，该电压大于位于第二绝缘层（8）的至少一部分的击穿电压半导体区域（10）和元件的导体区域（20）。施加编程电压，使得半导体区域（10）中的多数电荷载流子被吸引到半导体区域（10）和绝缘层（8）之间的界面（4）上，形成蓄积层（31）那里。另一方面，在剩余的列和导体之间，以相反的极性提供编程电压。因此，如果需要，可以仅通过单个电压电平VPROG来进行矩阵的编程。

3. 发明授权

US07786506B2 Semiconductor devices with a field shaping region 有权
标题翻译：具有场成形区域的半导体器件
公开(公告)号：US07786506B2
公开(公告)日：2010-08-31
申请号：US12177258
申请日：2008-07-22
申请人： Anco Heringa , Raymond J. E. Hueting , Jan W. Slotboom
发明人： Anco Heringa , Raymond J. E. Hueting , Jan W. Slotboom
IPC分类号： H01L29/74
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/408 , H01L29/73 , H01L29/732 , H01L29/7811 , H01L29/7813 , H01L29/7824 , H01L29/861
摘要： A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.
摘要翻译：半导体器件包括具有pn结的半导体区域和位于pn结附近的场整形区域，以增加器件的反向击穿电压。场整形区域经由电容性电压耦合区域耦合到与施加到pn结的基本相同的电压。当在pn结上施加反向电压并且器件不导通时，在场成形区域的一部分中存在电容电场，其延伸超过不存在pn结区域的pn结耗尽区的极限场整形区域。场成形区域中的电场引起限制在半导体区域中相应延伸的pn结耗尽区的拉伸电场。

4. 发明授权

US06436785B1 Method of manufacturing semiconductor device with a tunnel diode 有权
公开(公告)号：US06436785B1
公开(公告)日：2002-08-20
申请号：US09832724
申请日：2001-04-11
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Wiebe B. De Boer , Jan W. Slotboom
IPC分类号： H01L2120
摘要： A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions (2A, 3A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×1019 or even more than 1020 at/cm3. A simple method of manufacturing such a device is preferably done at a temperature between 550° C. and 800° C.

5. 发明授权

US4907049A Charge-coupled semiconductor device having an improved electrode structure 失效
标题翻译：具有改进的电极结构的电荷耦合半导体器件
公开(公告)号：US4907049A
公开(公告)日：1990-03-06
申请号：US385928
申请日：1989-07-27
申请人： Jan W. Slotboom , Henricus G. R. Maas , Kazimierz Osinki , Geert J. T. Davids
发明人： Jan W. Slotboom , Henricus G. R. Maas , Kazimierz Osinki , Geert J. T. Davids
IPC分类号： H01L29/762 , H01L21/339 , H01L27/10 , H01L29/423 , H01L29/76 , H01L29/772
CPC分类号： H01L29/66954 , H01L29/42396
摘要： A charge-coupled semiconductor device has a plurality of silicon electrodes for storing and transporting information-carrying charge, which electrodes are located on an insulating layer and are mutually separated by grooves having a width of at most 1 .mu.m. According to the invention, transfer electrodes are arranged in the grooves, these electrodes being coplanar with the remaining electrodes. The thickness of the insulating layer under the transfer electrodes is substantially equal to that under the storage electrodes. The invention also relates to a method of manufacturing a semiconductor device having such an electrode system.
摘要翻译：电荷耦合半导体器件具有用于存储和传送信息传送电荷的多个硅电极，这些电极位于绝缘层上并且由宽度至多为1μm的沟槽相互分离。根据本发明，转移电极布置在凹槽中，这些电极与剩余的电极共面。传输电极下面的绝缘层的厚度基本上等于存储电极下方的厚度。本发明还涉及制造具有这种电极系统的半导体器件的方法。

6. 发明授权

US4504930A Charge-coupled device 失效
标题翻译：电荷耦合器件
公开(公告)号：US4504930A
公开(公告)日：1985-03-12
申请号：US414109
申请日：1982-09-02
申请人： Hendrik A. Harwig , Jan W. Slotboom , Marcellinus J. M. Pelgrom
发明人： Hendrik A. Harwig , Jan W. Slotboom , Marcellinus J. M. Pelgrom
IPC分类号： G11C27/04 , G11C19/28 , H01L21/339 , H01L27/105 , H01L29/762 , G11C13/00
CPC分类号： H01L27/1057 , G11C19/287
摘要： The invention relates to a charge-coupled SPS memory comprising a series input register, a parallel section and a series output register. In order to increase the retention time leakage current drain regions are provided beside the memory. Since the charge collected as a result of leakage current is largest during the transport through the outermost registers of the parallel section, only the sides of the parallel section are screened by the said draining regions which preferably consist of dummy registers. FIG. 1.
摘要翻译：本发明涉及一种电荷耦合SPS存储器，其包括串联输入寄存器，并联部分和串联输出寄存器。为了增加保持时间，泄漏电流漏极区域设置在存储器的旁边。由于在通过并行部分的最外面寄存器的传输期间由于泄漏电流而收集的电荷最大，所以平行部分的侧面仅由虚拟寄存器组成的排水区域进行屏蔽。图。 1。

7. 发明授权

US08362821B2 Charge carrier stream generating electronic device and method 有权
标题翻译：电荷载流子流生成电子器件及方法
公开(公告)号：US08362821B2
公开(公告)日：2013-01-29
申请号：US12743400
申请日：2008-11-12
申请人： Tony Vanhoucke , Godefridus A. M. Hurkx , Jan W. Slotboom
发明人： Tony Vanhoucke , Godefridus A. M. Hurkx , Jan W. Slotboom
IPC分类号： H03K17/00 , H03K17/60
CPC分类号： G11C13/0004
摘要： An electronic device comprising a generator for generating a stream of charge carriers. The generator comprises a bipolar transistor having an emitter region, a collector region and a base region oriented between the emitter region and the collector region, and a controller for controlling exposure of the bipolar transistor to a voltage in excess of its open base breakdown voltage (BVCEO) such that the emitter region generates the stream of charge carriers from a first area being smaller than the emitter region surface area. The electronic device may further comprise a material arranged to receive the stream of charge carriers for triggering a change in a property of said material, the emitter region being arranged between the base region and the material.
摘要翻译：一种电子设备，包括用于产生电荷载流子的发生器。发生器包括双极晶体管，其具有发射极区域，集电极区域和定向在发射极区域和集电极区域之间的基极区域;以及控制器，用于控制双极晶体管的暴露于超过其开路基极击穿电压的电压（ BVCEO），使得发射极区域从小于发射极区域表面积的第一区域产生电荷载流子。电子设备还可以包括布置成接收电荷载流子的材料，用于触发所述材料的性质的变化，发射极区域布置在基底区域和材料之间。

8. 发明申请

US20100038676A1 Semiconductor Devices with a Field Shaping Region 有权
标题翻译：具有场成形区域的半导体器件
公开(公告)号：US20100038676A1
公开(公告)日：2010-02-18
申请号：US12177258
申请日：2008-07-22
申请人： Anco Heringa , Raymond J.E. Hueting , Jan W. Slotboom
发明人： Anco Heringa , Raymond J.E. Hueting , Jan W. Slotboom
IPC分类号： H01L29/74
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/408 , H01L29/73 , H01L29/732 , H01L29/7811 , H01L29/7813 , H01L29/7824 , H01L29/861
摘要： A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.
摘要翻译：半导体器件包括具有pn结的半导体区域和位于pn结附近的场整形区域，以增加器件的反向击穿电压。场整形区域经由电容性电压耦合区域耦合到与施加到pn结的基本相同的电压。当在pn结上施加反向电压并且器件不导通时，在场成形区域的一部分中存在电容电场，其延伸超过不存在pn结区域的pn结耗尽区的极限场整形区域。场成形区域中的电场引起限制在半导体区域中相应延伸的pn结耗尽区的拉伸电场。

9. 发明申请

US20080258182A1 Bicmos Compatible Jfet Device and Method of Manufacturing Same 审中-公开
标题翻译： Bicmos兼容Jfet设备及其制造方法相同
公开(公告)号：US20080258182A1
公开(公告)日：2008-10-23
申请号：US11577311
申请日：2005-10-13
申请人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
发明人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
IPC分类号： H01L29/808 , H01L21/8232 , H01L21/337
CPC分类号： H01L27/098 , H01L21/8248 , H01L27/0623
摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
摘要翻译：一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

10. 发明申请

US20080144355A1 Dielectric Antifuse for Electro-Thermally Programmable Device 有权
标题翻译：电热可编程器件介质防腐剂
公开(公告)号：US20080144355A1
公开(公告)日：2008-06-19
申请号：US11720320
申请日：2005-11-24
申请人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
发明人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
IPC分类号： G11C17/18 , G11C11/00 , H01L21/326 , H01L29/02
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径，用作编程材料的微小电加热器。由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。因此，编程功率可能很低。

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