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1. 发明授权

US07583774B2 Clock synchroniser 有权
标题翻译：时钟同步器
公开(公告)号：US07583774B2
公开(公告)日：2009-09-01
申请号：US10986994
申请日：2004-11-15
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03D3/18
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. Preferably, the clock comparison circuit compares the periods of the local and received clock signals.
摘要翻译：用于产生与所接收的时钟信号同步的本地时钟信号的时钟同步器与相应的时钟同步方法一起被描述和要求保护。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和远程时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。优选地，时钟比较电路比较本地和接收的时钟信号的周期。

2. 发明申请

US20050281367A1 Clock synchroniser 有权
标题翻译：时钟同步器
公开(公告)号：US20050281367A1
公开(公告)日：2005-12-22
申请号：US10986994
申请日：2004-11-15
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03D3/18 , H03L7/08 , H03L7/087 , H03L7/18 , H03L7/197 , H04L7/00 , H04L7/02
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchroniser, for generating a local clock signal synchronised to a received clock signal, is described and claimed, along with a corresponding clock synchronisation method. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. Preferably, the clock comparison circuit compares the periods of the local and received clock signals.
摘要翻译：用于产生与所接收的时钟信号同步的本地时钟信号的时钟同步器与相应的时钟同步方法一起被描述和要求保护。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和远程时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。优选地，时钟比较电路比较本地和接收的时钟信号的周期。

3. 发明申请

US20050220240A1 Clock synchroniser and clock and data recovery apparatus and method 审中-公开
标题翻译：时钟同步器和时钟与数据恢复装置及方法
公开(公告)号：US20050220240A1
公开(公告)日：2005-10-06
申请号：US10900347
申请日：2004-07-28
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： G06F5/06 , G06F5/12 , H03L7/10 , H03L7/197 , H04J3/06 , H04L7/00 , H04L7/033 , H04L25/05
CPC分类号： H03L7/197 , G06F5/06 , G06F5/12 , G06F2205/061 , H03L7/10 , H04J3/0632
摘要： A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser incorporates an elastic buffer. A received clock signal is used to clock data into the buffer, and a locally generated clock is used to clock data out of the buffer. The local clock is synthesised using a PLL, and a fill-level signal from the elastic buffer is used to control to local clock frequency to maintain a desired average quantity of data in the buffer, thereby achieving synchronisation of the received and local clocks. In preferred embodiments the fill-level signal is used to control a variable divider in the feedback path of the PLL, which is supplied with a highly stable reference signal. A synchronised, and low-jitter local clock is thus produced. Preferably, the elastic buffer employs counters of relatively wide word width, and a storage array of much reduced depth, read and write pointers being provided by just a few of the least significant bits of the words.
摘要翻译：时钟同步器以及并入时钟同步器的时钟和数据恢复装置与对应的时钟同步方法一起被描述。时钟同步器包含弹性缓冲器。接收到的时钟信号用于将数据进入缓冲器，本地生成的时钟用于将数据从缓冲器中提取出来。使用PLL合成本地时钟，并且使用来自弹性缓冲器的填充级信号来控制本地时钟频率，以保持缓冲器中期望的平均数据量，从而实现接收和本地时钟的同步。在优选实施例中，填充电平信号用于控制PLL的反馈路径中的可变分频器，其被提供有高度稳定的参考信号。因此产生了同步和低抖动的本地时钟。优选地，弹性缓冲器使用具有相对宽的字宽的计数器，并且由字的几个最低有效位提供了大大减少的深度，读和写指针的存储阵列。

4. 发明申请

US20110221487A1 CLOCK SYNCHRONISER 有权
标题翻译：时钟同步器
公开(公告)号：US20110221487A1
公开(公告)日：2011-09-15
申请号：US13113168
申请日：2011-05-23
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchroniser for generating a local clock signal synchronised to a received clock signal. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism.
摘要翻译：时钟同步器，用于产生与所接收的时钟信号同步的本地时钟信号。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和接收的时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。

5. 发明授权

US06856202B2 Phase/frequency detector and phase lock loop circuit 有权
标题翻译：相位/频率检测器和锁相环电路
公开(公告)号：US06856202B2
公开(公告)日：2005-02-15
申请号：US10459606
申请日：2003-06-12
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03L7/089 , H03L7/095 , H03L7/10 , H03L7/085 , H03D13/00
CPC分类号： H03L7/0891 , H03L7/095 , H03L7/10 , Y10S331/02
摘要： The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and to lock detectors for phase lock loop (PLL) circuits. The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; the cycle slip detector circuit comprising: means for determining a cycle slip between said input signals by determining when a delayed output signal coincides with a respective input signal.
摘要翻译：本发明涉及用于相位和频率检测器（PFD）的周期滑移检测器和用于锁定锁相环（PLL）电路的检测器。本发明提供了一种与具有第一和第二信号输入的相位和频率检测器电路一起使用的循环滑移检测器电路，并且被布置成分别响应于第一和第二输入信号中的时钟沿提供第一和第二PLL控制信号输出; 循环滑移检测器电路包括：用于通过确定延迟的输出信号何时与相应的输入信号一致来确定所述输入信号之间的周期滑移的装置。

6. 发明授权

US08537957B2 Clock synchroniser 有权
标题翻译：时钟同步器
公开(公告)号：US08537957B2
公开(公告)日：2013-09-17
申请号：US13113168
申请日：2011-05-23
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchronizer for generating a local clock signal synchronized to a received clock signal. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism.
摘要翻译：一种时钟同步器，用于产生与所接收的时钟信号同步的本地时钟信号。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和接收的时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。

7. 发明授权

US07949083B2 Clock synchroniser 有权
标题翻译：时钟同步器
公开(公告)号：US07949083B2
公开(公告)日：2011-05-24
申请号：US12533422
申请日：2009-07-31
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchronizer for generating a local clock signal synchronized to a received clock signal. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism.
摘要翻译：一种时钟同步器，用于产生与所接收的时钟信号同步的本地时钟信号。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和接收的时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。

8. 发明申请

US20100020912A1 CLOCK SYNCHRONISER 有权
标题翻译：时钟同步器
公开(公告)号：US20100020912A1
公开(公告)日：2010-01-28
申请号：US12533422
申请日：2009-07-31
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03D3/24 , H04L7/00
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchroniser, for generating a local clock signal synchronised to a received clock signal, is described and claimed, along with a corresponding clock synchronisation method. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism. Preferably, the clock comparison circuit compares the periods of the local and received clock signals.
摘要翻译：用于产生与所接收的时钟信号同步的本地时钟信号的时钟同步器与相应的时钟同步方法一起被描述和要求保护。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和远程时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。优选地，时钟比较电路比较本地和接收的时钟信号的周期。

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