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1. 发明授权

US09136755B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US09136755B2
公开(公告)日：2015-09-15
申请号：US13336835
申请日：2011-12-23
申请人： John Paul Lesso , Peter John Frith , John Laurence Pennock
发明人： John Paul Lesso , Peter John Frith , John Laurence Pennock
IPC分类号： G05F1/10 , G05F3/02 , H02M3/07
CPC分类号： H02M3/07 , H02M2003/071 , H02M2003/072 , H03G3/30
摘要： A bipolar output charge pump circuit having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN), two pairs of flying capacitor nodes (CF1A, CF1B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/−3VV, +/−VV/5 or +/−VV/6.
摘要翻译：一种双极性输出电荷泵电路，具有用于选择性地连接输入节点（VV）和用于连接到输入电压的参考节点（VG）的开关路径110的网络，第一对输出节点（VP，VN），两对的飞行电容器节点（CF1A，CF1B; CF2A，CF2B）和用于控制切换路径网络的切换的控制器。当与两对飞跨电容器节点连接的两个浮动电容器（CF1，CF2）使用时，该控制器可操作以控制开关路径网络，以在连接两个飞行电容器时提供第一模式和第二模式其中至少第一模式对应于+/- 3VV，+/- VV / 5或+/- VV / 6的双极性输出电压。

2. 发明申请

US20120170770A1 CHARGE PUMP CIRCUIT 有权
标题翻译：充电泵电路
公开(公告)号：US20120170770A1
公开(公告)日：2012-07-05
申请号：US13336835
申请日：2011-12-23
申请人： John Paul Lesso , Peter John Frith , John Laurence Pennock
发明人： John Paul Lesso , Peter John Frith , John Laurence Pennock
IPC分类号： H03G3/00 , H02B1/00 , G05F1/10
CPC分类号： H02M3/07 , H02M2003/071 , H02M2003/072 , H03G3/30
摘要： A bipolar output charge pump circuit having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN), two pairs of flying capacitor nodes (CF1A, CF1B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/−3VV, +/−VV/5 or +/−VV/6.
摘要翻译：一种双极性输出电荷泵电路，具有用于选择性地连接输入节点（VV）和用于连接到输入电压的参考节点（VG）的开关路径110的网络，第一对输出节点（VP，VN），两对的飞行电容器节点（CF1A，CF1B; CF2A，CF2B）和用于控制切换路径网络的切换的控制器。当与两对飞跨电容器节点连接的两个浮动电容器（CF1，CF2）使用时，该控制器可操作以控制开关路径网络，以在连接两个飞行电容器时提供第一模式和第二模式其中至少第一模式对应于+/- 3VV，+/- VV / 5或+/- VV / 6的双极性输出电压。

3. 发明申请

US20120163632A1 CHARGE PUMP CIRCUIT 有权
标题翻译：充电泵电路
公开(公告)号：US20120163632A1
公开(公告)日：2012-06-28
申请号：US13403450
申请日：2012-02-23
申请人： John Paul Lesso , Peter John Frith , John Laurence Pennock
发明人： John Paul Lesso , Peter John Frith , John Laurence Pennock
IPC分类号： H03G3/00 , G05F1/10
CPC分类号： H02M3/07 , H02M1/00 , H02M2001/0083 , H02M2001/009 , H03F3/181
摘要： A bipolar output charge pump circuit 100 having a network of switching paths 110 for selectively connecting an input node (VV) and a reference node (VG) for connection to an input voltage, a first pair of output nodes (VP, VN) and a second pair of output nodes (VQ, VM), and two pairs of flying capacitor nodes (CF1A, CF1 B; CF2A, CF2B), and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors (CF1, CF2) connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes (VP, VN) and a second bipolar output voltage at the second pair of bipolar output nodes (VQ, VM).
摘要翻译：具有用于选择性地连接输入节点（VV）和用于连接到输入电压的参考节点（VG）的开关路径网络的双极性输出电荷泵电路100，第一对输出节点（VP，VN）和第二对输出节点（VQ，VM）和两对飞电容器节点（CF1A，CF1B; CF2A，CF2B），以及用于控制切换路径网络切换的控制器。控制器可操作以在与两对飞跨电容器节点连接的两个飞行电容器（CF1，CF2）使用时控制开关路径网络，以在第一对输出节点（VP， VN）和在第二对双极输出节点（VQ，VM）处的第二双极性输出电压。

4. 发明授权

US08068623B2 Capacitive transducer circuit and method 有权
标题翻译：电容式传感器电路及方法
公开(公告)号：US08068623B2
公开(公告)日：2011-11-29
申请号：US12436909
申请日：2009-05-07
申请人： John Paul Lesso
发明人： John Paul Lesso
IPC分类号： H02B1/00
CPC分类号： G01P15/125 , B06B1/0292
摘要： A capacitive transducer circuit includes a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analog signal on an input terminal, the first analog signal being generated by the capacitive transducer, and to generate a second analog signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. A switched capacitor filter circuit may be arranged between the voltage source and the transducer and may be arranged to filter the output of the voltage source.
摘要翻译：电容式换能器电路包括具有第一和第二电极的电容换能器。第一和第二电极被相应的第一和第二偏置电压偏置。放大器被连接以在输入端子上接收第一模拟信号，第一模拟信号由电容式换能器产生，并在输出端产生第二模拟信号。数字反馈电路连接在放大器的输出端和放大器的输入端之间。数字反馈电路被配置为提供所述第一或第二偏置电压之一。开关电容器滤波器电路可以布置在电压源和换能器之间，并且可以被布置成对电压源的输出进行滤波。

5. 发明申请

US20110221487A1 CLOCK SYNCHRONISER 有权
标题翻译：时钟同步器
公开(公告)号：US20110221487A1
公开(公告)日：2011-09-15
申请号：US13113168
申请日：2011-05-23
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/197 , H04L7/0008 , H04L7/005
摘要： A clock synchroniser for generating a local clock signal synchronised to a received clock signal. The clock synchroniser incorporates a reference oscillator providing a reference signal, and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal. The synthesiser circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and received clock signals. A control link is arranged to link the clock comparison circuit to the divider. This link receives the digital signal and provides a control signal to the divider to adjust the frequency division value N according to the digital signal, to alter the local clock frequency and reduce the asynchronism.
摘要翻译：时钟同步器，用于产生与所接收的时钟信号同步的本地时钟信号。时钟同步器包括提供参考信号的参考振荡器和被配置为从参考信号合成本地时钟信号的合成器电路。合成器电路包括锁相环电路，包括接收参考信号的相位检测器和布置在从受控振荡器到相位检测器的反馈路径中的可控分频器，分频器可控制以分频值N 沿路径确定本地时钟频率与参考频率的比值。时钟同步器还包括适于产生指示本地和接收的时钟信号之间的异步的数字信号的时钟比较电路。控制链路被布置成将时钟比较电路链接到分频器。该链路接收数字信号，并向分频器提供控制信号以根据数字信号调整分频值N，以改变本地时钟频率并减少异步。

6. 发明申请

US20100219888A1 AMPLIFIER CIRCUIT 有权
标题翻译：放大器电路
公开(公告)号：US20100219888A1
公开(公告)日：2010-09-02
申请号：US12671639
申请日：2008-08-04
申请人： John Paul Lesso
发明人： John Paul Lesso
IPC分类号： H03G3/20
CPC分类号： H03G3/3015 , H03F1/0216 , H03F1/0227 , H03F1/0261 , H03F1/30 , H03F3/185 , H03F3/193 , H03F2200/03 , H03F2200/504 , H03G3/001
摘要： An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier, and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.
摘要翻译：放大器电路包括用于接收待放大的输入信号的输入端; 前置放大器，用于基于可变增益放大输入信号; 用于放大从前置放大器输出的信号的功率放大器和用于向功率放大器提供一个或多个电源电压的可变电压电源。电源电压根据可变增益或输入数字信号进行调整。根据本发明的其他方面，使用时钟信号对放大器电路的电源进行定时，由此时钟信号具有根据音量信号或输入信号而变化的频率。

7. 发明授权

US07649480B2 Calibration circuit and associated method 有权
标题翻译：校准电路及相关方法
公开(公告)号：US07649480B2
公开(公告)日：2010-01-19
申请号：US11987772
申请日：2007-12-04
申请人： Alastair Mark Boomer , John Paul Lesso
发明人： Alastair Mark Boomer , John Paul Lesso
IPC分类号： H03M1/10
CPC分类号： H03M1/1023 , H03M1/1009 , H03M1/12
摘要： A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.
摘要翻译：一种适用于图像处理中的黑电平校准的校准电路和方法，该电路包括模拟增益放大器，模数转换器; 用于接收数字信号并提供数字偏移信号的校正电路; 以及数模转换器，用于接收所述数字偏移信号，并将相应的模拟偏移信号反馈给所述增益放大器的输入端。校准电路被布置成使得校正电路和所述数模转换器形成对所述输入信号施加偏移的反馈环路，并且所述校正电路包括用于在所述校正电路之前对所述校正电路中的信号施加反增益的反相增益电路表示数模转换器。优选地，应用的反增益使得总环路增益不会偏离太远离单位。

8. 发明申请

US20090279719A1 CAPACITIVE TRANSDUCER CIRCUIT AND METHOD 有权
标题翻译：电容式传感器电路及方法
公开(公告)号：US20090279719A1
公开(公告)日：2009-11-12
申请号：US12436909
申请日：2009-05-07
申请人： John Paul Lesso
发明人： John Paul Lesso
IPC分类号： H04R11/04
CPC分类号： G01P15/125 , B06B1/0292
摘要： A capacitive transducer circuit includes a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analog signal on an input terminal, the first analog signal being generated by the capacitive transducer, and to generate a second analog signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. A switched capacitor filter circuit may be arranged between the voltage source and the transducer and may be arranged to filter the output of the voltage source.
摘要翻译：电容式换能器电路包括具有第一和第二电极的电容换能器。第一和第二电极被相应的第一和第二偏置电压偏置。放大器被连接以在输入端子上接收第一模拟信号，第一模拟信号由电容换能器产生，并在输出端产生第二模拟信号。数字反馈电路连接在放大器的输出端和放大器的输入端之间。数字反馈电路被配置为提供所述第一或第二偏置电压之一。开关电容器滤波器电路可以布置在电压源和换能器之间，并且可以被布置成对电压源的输出进行滤波。

9. 发明授权

US06856202B2 Phase/frequency detector and phase lock loop circuit 有权
标题翻译：相位/频率检测器和锁相环电路
公开(公告)号：US06856202B2
公开(公告)日：2005-02-15
申请号：US10459606
申请日：2003-06-12
申请人： Paul Lesso
发明人： Paul Lesso
IPC分类号： H03L7/089 , H03L7/095 , H03L7/10 , H03L7/085 , H03D13/00
CPC分类号： H03L7/0891 , H03L7/095 , H03L7/10 , Y10S331/02
摘要： The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and to lock detectors for phase lock loop (PLL) circuits. The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; the cycle slip detector circuit comprising: means for determining a cycle slip between said input signals by determining when a delayed output signal coincides with a respective input signal.
摘要翻译：本发明涉及用于相位和频率检测器（PFD）的周期滑移检测器和用于锁定锁相环（PLL）电路的检测器。本发明提供了一种与具有第一和第二信号输入的相位和频率检测器电路一起使用的循环滑移检测器电路，并且被布置成分别响应于第一和第二输入信号中的时钟沿提供第一和第二PLL控制信号输出; 循环滑移检测器电路包括：用于通过确定延迟的输出信号何时与相应的输入信号一致来确定所述输入信号之间的周期滑移的装置。

10. 发明授权

US08913762B2 Capacitive transducer circuit and method 有权
标题翻译：电容式传感器电路及方法
公开(公告)号：US08913762B2
公开(公告)日：2014-12-16
申请号：US12812390
申请日：2009-05-07
申请人： Colin Findlay Steele , Goran Stojanovic , John Paul Lesso
发明人： Colin Findlay Steele , Goran Stojanovic , John Paul Lesso
IPC分类号： H03M1/00 , G01D3/032 , G01D5/24 , H04R3/00 , H04R19/00 , H04R19/04
CPC分类号： G01D5/24 , G01D3/032 , H04R3/00 , H04R19/005 , H04R19/04
摘要： A capacitive transducer circuit comprises a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analog signal on an input terminal, the first analog signal being generated by the capacitive transducer, and to generate a second analog signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. The output of a voltage source which provides the other bias voltage for the capacitive transducer may be filtered by a low pass filter. The low pass filter may comprise a switched capacitor filter circuit.
摘要翻译：电容式换能器电路包括具有第一和第二电极的电容换能器。第一和第二电极被相应的第一和第二偏置电压偏置。放大器被连接以在输入端子上接收第一模拟信号，第一模拟信号由电容换能器产生，并在输出端产生第二模拟信号。数字反馈电路连接在放大器的输出端和放大器的输入端之间。数字反馈电路被配置为提供所述第一或第二偏置电压之一。提供电容换能器的另一个偏置电压的电压源的输出可以被低通滤波器滤波。低通滤波器可以包括开关电容滤波器电路。

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