专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11960446B2 Video content graph including enhanced metadata 有权
公开(公告)号：US11960446B2
公开(公告)日：2024-04-16
申请号：US17315537
申请日：2021-05-10
申请人： Home Box Office, Inc.
发明人： Gregory John Bellingham , William A. McNamara , Brandon C. Furtwangler
IPC分类号： G06F16/16 , G06F5/12 , H04N21/235 , H04N21/236 , H04N21/4722 , H04N21/482 , H04N21/84 , H04N21/845 , H04N21/858 , H04L65/70
CPC分类号： G06F16/164 , G06F5/12 , H04N21/235 , H04N21/236 , H04N21/23614 , H04N21/4722 , H04N21/4828 , H04N21/84 , H04N21/8456 , H04N21/858 , H04L65/70
摘要： The described technology is directed towards sending metadata related to a video to a client device, such as events that describe a portion of that video, such as in a hidden stream. In one or more implementations, the enhanced metadata comprises nodes used to build part of a relationship graph. This allows interested clients to switch between the feature playback and interacting with the metadata. Further, searches through the enhanced metadata may be performed to find matching video portions, and summaries or highlights of one or more videos may be assembled by accessing information in the enhanced metadata.

2. 发明授权

US11822815B2 Handling ring buffer updates 有权
公开(公告)号：US11822815B2
公开(公告)日：2023-11-21
申请号：US17310868
申请日：2020-02-25
申请人： Arm Limited
发明人： Eric Ola Harald Liljedahl
IPC分类号： G06F3/06 , G06F5/12
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0631 , G06F3/0659 , G06F3/0679 , G06F5/12
摘要： Ring buffer storage circuitry is disclosed which stores a ring buffer comprising multiple slots to hold a queued se-quence of data items. Data processing circuitry executes a plurality of processes to add one or more data items to be processed to the queued sequence and to remove one or more data items for process-ing from the queued sequence. Each process is arranged to perform an acquire process to acquire at least one slot in the ring buffer and to subsequently perform a release process to release the at least one slot. Ring buffer metadata storage circuitry stores metadata for the ring buffer comprising a first reference indicator and a second reference indicator. Corresponding methods and instructions are also disclosed.

3. 发明授权

US10645279B2 Imaging element, imaging apparatus, and control method for imaging element 有权
公开(公告)号：US10645279B2
公开(公告)日：2020-05-05
申请号：US16092366
申请日：2016-12-29
申请人： Sony Corporation
发明人： Masao Zen , Jun Hashizume , Tsutomu Nakajima , Norihiro Ichimaru
IPC分类号： H04N5/232 , G06T1/60 , G06F5/06 , G06F5/12 , G06F12/02 , H04N5/351 , H04N5/353
CPC分类号： H04N5/23232 , G06F5/065 , G06F5/12 , G06F12/023 , G06T1/60 , H04N5/23245 , H04N5/351 , H04N5/353
摘要： An imaging apparatus including a frame buffer executes high-speed shooting consecutively in plural sessions.
An imaging element includes a buffer, an image producing unit, a managing unit, and an output unit. The image producing unit produces an image in the case where an empty capacity of any of plural areas in the buffer exceeds a predetermined threshold value. The managing unit causes an area whose empty capacity exceeds the predetermined threshold value, of the plural areas to retain the image as a buffering image. The output unit extracts the buffering image from the buffer and outputting the buffering image, in order of the retention of the buffering image.

4. 发明申请

US20180081848A1 RECEIVING BUFFER CREDITS BY A PLURALITY OF CHANNELS OF ONE OR MORE HOST COMPUTATIONAL DEVICES FOR TRANSMITTING DATA TO A CONTROL UNIT 审中-公开
公开(公告)号：US20180081848A1
公开(公告)日：2018-03-22
申请号：US15826474
申请日：2017-11-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Roger G. Hathorn , Bret W. Holley , Matthew J. Kalos
IPC分类号： G06F13/40 , H04L12/801 , G06F3/06 , G06F13/16 , G06F5/12 , G06F13/36
CPC分类号： G06F13/4027 , G06F3/0613 , G06F3/0656 , G06F3/067 , G06F5/12 , G06F13/1642 , G06F13/1673 , G06F13/36 , G06F2003/0691 , G06F2205/126 , G06F2213/0008 , H04L47/39
摘要： A channel of a host computational device sends a command to transfer data to a control unit included in a storage controller. The channel of the host computational device receives a number of buffer credits from the control unit for communication with the control unit, where the number of buffer credits that is received is based on the control unit monitoring a number of transfer ready operations and a number of retry operations during a monitoring period while communicating with a plurality of channels that includes the channel.

5. 发明申请

US20170293519A1 METHOD AND SYSTEM FOR TIMEOUT MONITORING 审中-公开
公开(公告)号：US20170293519A1
公开(公告)日：2017-10-12
申请号：US15631544
申请日：2017-06-23
申请人： Infineon Technologies AG
发明人： Karl Herz , Ljudmil Anastasov , Harald Zweck
IPC分类号： G06F11/07 , G06F11/34 , G06F11/30
CPC分类号： G06F11/0757 , G06F5/065 , G06F5/12 , G06F11/0721 , G06F11/0745 , G06F11/079 , G06F11/3024 , G06F11/3027 , G06F11/3495 , G06F13/4282
摘要： Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

6. 发明授权

US09727400B2 Method and system for timeout monitoring 有权
公开(公告)号：US09727400B2
公开(公告)日：2017-08-08
申请号：US14881496
申请日：2015-10-13
申请人： Infineon Technologies AG
发明人： Karl Herz , Ljudmil Anastasov , Harald Zweck
IPC分类号： G01R31/08 , G06F11/07 , G06F5/06 , G06F5/12 , G06F11/30 , G06F13/42
CPC分类号： G06F11/0757 , G06F5/065 , G06F5/12 , G06F11/0721 , G06F11/0745 , G06F11/079 , G06F11/3024 , G06F11/3027 , G06F11/3495 , G06F13/4282
摘要： Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.

7. 发明申请

US20170168755A1 SOFTWARE DEFINED FIFO BUFFER FOR MULTITHREADED ACCESS 审中-公开
公开(公告)号：US20170168755A1
公开(公告)日：2017-06-15
申请号：US14966631
申请日：2015-12-11
申请人： Vivante Corporation
发明人： Mankit Lo
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F5/12
摘要： A computer system includes a hardware buffer controller. Memory access requests to a buffer do not include an address within the buffer and threads accessing the buffer do not access or directly update any pointers to locations within the buffer. The memory access requests are addressed to the hardware buffer controller, which determines an address from its current state and issues a memory access command to that address. The hardware buffer controller updates its state in response to the memory access requests. The hardware buffer controller evaluates its state and outputs events to a thread scheduler in response to overflow or underflow conditions or near-overflow or near-underflow conditions. The thread scheduler may then block threads from issuing memory access requests to the hardware buffer controller. The buffer implemented may be a FIFO or other type of buffer.

8. 发明授权

US09680773B1 Integrated circuit with dynamically-adjustable buffer space for serial interface 有权
公开(公告)号：US09680773B1
公开(公告)日：2017-06-13
申请号：US13245790
申请日：2011-09-26
申请人： Zun Yang Tan , Tat Mun Lui , Boon Jin Ang , Chiang Wei Lee , Richard Jin Guan Saw , Want Sent Khor
发明人： Zun Yang Tan , Tat Mun Lui , Boon Jin Ang , Chiang Wei Lee , Richard Jin Guan Saw , Want Sent Khor
IPC分类号： H04L12/861 , G06F5/12 , G06F1/32 , G11C5/14
CPC分类号： H04L49/9005 , G06F1/3225 , G06F1/3243 , G06F1/3275 , G06F1/3278 , G06F1/3287 , G06F5/12 , G11C5/148 , Y02D10/14 , Y02D10/157
摘要： One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.

9. 发明授权

US09658822B1 Rate controlled buffer for output at either a first or second rate responsive to a fill level 有权
公开(公告)号：US09658822B1
公开(公告)日：2017-05-23
申请号：US14566962
申请日：2014-12-11
申请人： Xilinx, Inc.
发明人： Niall J. O'Connor , Amrish J. Patel , William G. Dalzell
IPC分类号： G06F3/00 , G06F5/14
CPC分类号： G06F5/14 , G06F5/12 , G06F2205/126
摘要： Buffer rate control generally relates to outputting data at either a first rate or a second rate responsive to a fill level of the buffer. In an apparatus therefore, there is a buffer for receiving a data-signal input and for providing a data-signal output. A controller is coupled to receive fill-level information from the buffer and coupled to provide rate-control information to the buffer. The rate-control information is for controlling an output rate of the buffer for the data-signal output to be provided to a bus. The output rate is either a first rate or a second rate for providing the output rate of the data-signal output to the bus. The fill-level information is for selecting either the first rate or the second rate responsive to the buffer being either above or below a threshold fill level, respectively.

10. 发明授权

US09594396B2 Synchronizing data transfer between a first clock domain and second clock domain 有权
标题翻译：在第一个时钟域和第二个时钟域之间同步数据传输
公开(公告)号：US09594396B2
公开(公告)日：2017-03-14
申请号：US13703582
申请日：2011-07-26
申请人： Edward James Turner , Jon Beecroft
发明人： Edward James Turner , Jon Beecroft
IPC分类号： G06F1/12 , G06F5/12 , H04L7/02
CPC分类号： G06F1/12 , G06F5/12 , H04L7/02
摘要： A data processing system comprises a first clock domain having a first clock rate, a second clock domain having a second clock rate, and a data path operable to transfer data items from the first clock domain to the second clock domain. The data path comprises a buffer having an input for receiving data items from the first clock domain, and an output port for transmitting data items to the second clock domain in a first-in first-out manner. The buffer has a first pointer for indication of a current first location of the buffer, and a second pointer for indication of a current second location of the buffer. The system further includes a read controller operable to define a read pattern for the buffer, to control output from the buffer in dependence upon such a read pattern, and to adjust such a read pattern in dependence upon a value of such a first pointer for the buffer.
摘要翻译：数据处理系统包括具有第一时钟速率的第一时钟域，具有第二时钟速率的第二时钟域和可操作以将数据项从第一时钟域传送到第二时钟域的数据路径。数据路径包括具有用于从第一时钟域接收数据项的输入的缓冲器和用于以先进先出的方式将数据项发送到第二时钟域的输出端口。缓冲器具有用于指示缓冲器的当前第一位置的第一指针和用于指示缓冲器的当前第二位置的第二指示器。该系统还包括读取控制器，其可操作以定义缓冲器的读取模式，以依赖于这种读取模式来控制来自缓冲器的输出，并且根据这样的第一指针的值来调整这样的读取模式缓冲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式