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1. 发明授权

US09672008B2 Pausible bisynchronous FIFO 有权
公开(公告)号：US09672008B2
公开(公告)日：2017-06-06
申请号：US14948175
申请日：2015-11-20
申请人： NVIDIA Corporation
发明人： Benjamin Andrew Keller , Matthew Rudolph Fojtik , Brucek Kurdo Khailany
IPC分类号： G11C7/00 , G06F5/06 , G11C7/22 , G11C8/16
CPC分类号： G06F5/06 , G06F2205/061 , G11C7/222 , G11C8/16 , G11C2207/2254 , G11C2207/2272
摘要： A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.

2. 发明授权

US09491332B2 Clock transfer circuit, video processing system, and semiconductor integrated circuit 有权
标题翻译：时钟传输电路，视频处理系统和半导体集成电路
公开(公告)号：US09491332B2
公开(公告)日：2016-11-08
申请号：US14553541
申请日：2014-11-25
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： Yuuki Nishio
IPC分类号： H04N5/08 , H04N7/01 , G06F5/06 , G09G5/00 , H04N21/43 , H04N21/436 , H04N21/4363
CPC分类号： H04N5/08 , G06F5/06 , G06F2205/061 , G09G5/005 , G09G5/006 , G09G2340/0435 , G09G2370/10 , H04N7/0105 , H04N21/4305 , H04N21/43632
摘要： A clock transfer circuit receives input data synchronized with a first clock, and outputs, as output data, data synchronized with a second clock having a frequency different from that of the first clock. A write address controller is operating according to the first clock, and provides a write address to a memory. A read address controller is operating according to the second clock, and provides a read address to the memory. A cycle comparator compares the cycle of a predetermined event between the input data and the output data. Based on such a comparison result, the clock adjuster adjusts the frequency of the second clock.
摘要翻译：时钟传送电路接收与第一时钟同步的输入数据，并且输出与具有与第一时钟不同的频率的第二时钟同步的数据作为输出数据。写地址控制器根据第一时钟进行操作，并向存储器提供写地址。读地址控制器根据第二时钟进行操作，并向存储器提供读地址。循环比较器比较输入数据和输出数据之间的预定事件的周期。基于这样的比较结果，时钟调整器调节第二时钟的频率。

3. 发明授权

US09250859B2 Deterministic FIFO buffer 有权
标题翻译：确定性FIFO缓冲区
公开(公告)号：US09250859B2
公开(公告)日：2016-02-02
申请号：US14158439
申请日：2014-01-17
申请人： ALTERA CORPORATION
发明人： David W. Mendel , Dana How
IPC分类号： G06F3/00 , G06F5/00 , G06F5/14 , G06F5/12
CPC分类号： G06F5/14 , G06F5/12 , G06F2205/061
摘要： One embodiment relates to a method for determining a latency of a FIFO buffer. A highest-order bit is provided from FIFO write and read counters to input-comparison logic that distinguishes between the highest-order write and read bits having a same logic level and the highest-order write and read bits having different logic levels. The occupancy level, and hence the latency, of the FIFO buffer is determined based on the output of the input-comparison logic. Another embodiment relates to a FIFO buffer having write and read counters that each have a length in bits that is one bit longer than is needed to address the FIFO buffer. Another embodiment relates to a method of tuning a latency of a FIFO buffer. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种用于确定FIFO缓冲器的等待时间的方法。从FIFO写入和读取计数器到输入比较逻辑提供了一个最高位，以区分具有相同逻辑电平的最高位写入位和读取位以及具有不同逻辑电平的最高位写入和读取位。基于输入比较逻辑的输出来确定FIFO缓冲器的占用水平，因此等待时间。另一个实施例涉及一种具有写入和读出计数器的FIFO缓冲器，其每一个具有比寻址FIFO缓冲器所需的位长一位的位长度。另一个实施例涉及一种调整FIFO缓冲器等待时间的方法。还公开了其它实施例和特征。

4. 发明申请

US20120303994A1 APPARATUS FOR SYNCHRONIZING A DATA HANDOVER BETWEEN A FIRST CLOCK DOMAIN AND A SECOND CLOCK DOMAIN 有权
标题翻译：用于同步第一时钟域和第二时钟域之间的数据切换的装置
公开(公告)号：US20120303994A1
公开(公告)日：2012-11-29
申请号：US13113730
申请日：2011-05-23
申请人： Thomas Bauernfeind , Stephan Henzler
发明人： Thomas Bauernfeind , Stephan Henzler
IPC分类号： G06F13/42 , H04L7/00
CPC分类号： H04L7/005 , G06F5/12 , G06F2205/061 , G06F2205/102 , H04L7/0012
摘要： Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is clocked with the clock of the first clock domain and configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage is configured to take over an input data value in synchronization with the first clock domain and to provide an output data value in synchronization with the second clock domain and in response to a current synchronization pulse. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the subsequent synchronization pulse such that the subsequent synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The fill level information provider is configured to provide a fill level information describing a fill level of the first-in-first-out storage. The feedback path is configured for feeding back the fill level information to the calculator that is further configured to adjust the synchronization pulse cycle duration information based on the fill level information.
摘要翻译：本发明的实施例提供了一种用于在第一时钟域和第二时钟域之间同步数据切换的装置。该装置包括计算器，先进先出存储器，同步脉冲发生器，填充级信息提供器和反馈路径。计算器用第一时钟域的时钟计时，并且被配置为提供描述在第二时钟域的时钟处的同步脉冲的时间位置的同步脉冲周期持续时间信息。先入先出存储被配置为与第一时钟域同步地接收输入数据值，并且响应于当前同步脉冲提供与第二时钟域同步的输出数据值。同步脉冲发生器用第二时钟域的时钟计时，并被配置为产生后续的同步脉冲，使得随后的同步脉冲位于由同步脉冲周期持续时间信息描述的时间位置。填充级别信息提供者被配置为提供描述先进先出存储器的填充级别的填充级别信息。反馈路径被配置为将填充水平信息反馈到计算器，该计算器还被配置为基于填充水平信息来调整同步脉冲周期持续时间信息。

5. 发明授权

US08095816B1 Processor management using a buffer 有权
公开(公告)号：US08095816B1
公开(公告)日：2012-01-10
申请号：US12098254
申请日：2008-04-04
申请人： Ting Li Chan , Fredarico E. Dutton
发明人： Ting Li Chan , Fredarico E. Dutton
IPC分类号： G06F1/32 , G06F1/00 , G06F5/00
CPC分类号： G06F5/12 , G06F1/3209 , G06F1/3237 , G06F1/3287 , G06F2205/061 , G06F2205/126 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

6. 发明授权

US08014281B1 Systems and methods for limiting the rates of data to/from a buffer 有权
标题翻译：用于限制缓冲区数据的速率的系统和方法
公开(公告)号：US08014281B1
公开(公告)日：2011-09-06
申请号：US12605421
申请日：2009-10-26
申请人： Raymond Marcelino Manese Lim , Song Zhang , Anurag P. Gupta , Brian Gaudet
发明人： Raymond Marcelino Manese Lim , Song Zhang , Anurag P. Gupta , Brian Gaudet
IPC分类号： G06F11/00 , H04L12/26 , H04L12/43
CPC分类号： G06F5/06 , G06F2205/061
摘要： A system controls the transfer of data. The system receives a request to transfer data and determines whether a counter value equals or exceeds a threshold. The counter value represents an amount of time since a previous data transfer. When the counter value equals or exceeds the threshold, the system transmits the data. In another implementation, the system tracks the amount of data read from a buffer. The system reduces the speed at which data is read when the amount of data read from the buffer exceeds a threshold.
摘要翻译：系统控制数据传输。系统接收传送数据的请求，并确定计数器值是否等于或超过阈值。计数器值表示自先前数据传输以来的时间量。当计数器值等于或超过阈值时，系统发送数据。在另一个实现中，系统跟踪从缓冲器读取的数据量。当从缓冲区读取的数据量超过阈值时，系统会降低读取数据的速度。

7. 发明授权

US08001297B2 Dynamic adjusting send rate of buffered data 有权
标题翻译：缓冲数据的动态调整发送速率
公开(公告)号：US08001297B2
公开(公告)日：2011-08-16
申请号：US11114310
申请日：2005-04-25
申请人： Michael D. Volodarsky , Patrick Yu-Kwan Ng
发明人： Michael D. Volodarsky , Patrick Yu-Kwan Ng
IPC分类号： G06F5/00
CPC分类号： G06F5/06 , G06F2205/061
摘要： Systems and methods for intermediate buffering of data for the purpose of controlling its delivery to the consumer. The systems and methods for buffering data can arbitrate between the incoming data flow from the generating component and the outgoing data flow to the consumer. In doing so, the systems and methods for buffering of data seek to honor the delivery demands and/or constraints of the consumer, while avoiding the loss of the data generated by the producer. The delivery demands of the consumer may include requirements pertaining to maximum acceptable incoming data rate, the desired incoming data rate, incoming data aggregation, the desired freshness of the data, and tolerance for event loss. The generation component constraints may include the space limitations on buffering data within the data buffer.
摘要翻译：用于中间缓冲数据的系统和方法，用于控制其传送给消费者。用于缓冲数据的系统和方法可以在来自生成组件的输入数据流和到消费者的输出数据流之间进行仲裁。在这样做时，用于缓冲数据的系统和方法旨在满足消费者的传递需求和/或限制，同时避免生产者生成的数据的丢失。消费者的传送需求可以包括关于最大可接受的输入数据速率，期望的输入数据速率，输入数据聚合，期望的数据新鲜度和事件丢失容限的要求。生成组件约束可以包括对数据缓冲器内的缓冲数据的空间限制。

8. 发明授权

US07995622B1 Digital clock smoothing 失效
标题翻译：数字时钟平滑
公开(公告)号：US07995622B1
公开(公告)日：2011-08-09
申请号：US12587266
申请日：2009-10-05
申请人： Richard John Fagerlund , James P. Flynn , Mark Fong , David Bruce Isaksen
发明人： Richard John Fagerlund , James P. Flynn , Mark Fong , David Bruce Isaksen
IPC分类号： H04J3/06 , H04L7/00
CPC分类号： G06F5/06 , G06F2205/061
摘要： A method for digital clock smoothing is provided. The method comprises: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting FIFO depth B into a programmable look-up table (LUT); (D) obtaining a phase detector error signal; (E) scaling the phase detector error signal to obtain a scaled error factor; (F) adding the scaled error factor to a nominal phase step to obtain a phase update; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from FIFO under control of an output FIFO address control register at the smoothed symbol rate.
摘要翻译：提供了一种用于数字时钟平滑的方法。该方法包括：（A）将具有异步符号速率的异步数据流输入到FIFO双端口存储器块中; （B）通过从符号输入地址减去每个存储符号的符号输出地址的模B来获得FIFO深度B; （C）将FIFO深度B输入到可编程查询表（LUT）中; （D）获得相位检测器误差信号; （E）缩放相位检测器误差信号以获得缩放误差因子; （F）将缩放的误差因子加到标称相位步长以获得相位更新; （G）获得平滑符号率; 和（H）以平滑符号速率在输出FIFO地址控制寄存器的控制下从FIFO读出每个输出符号。

9. 发明授权

US07366270B2 PLL/DLL dual loop data synchronization utilizing a granular FIFO fill level indicator 有权
标题翻译： PLL / DLL双循环数据同步利用粒度FIFO填充水平指示器
公开(公告)号：US07366270B2
公开(公告)日：2008-04-29
申请号：US10029709
申请日：2001-12-20
申请人： Benjamin Tang , Scott Southwell , Nicholas Robert Steffen
发明人： Benjamin Tang , Scott Southwell , Nicholas Robert Steffen
IPC分类号： H04L7/00 , H03D3/24 , H03L7/00
CPC分类号： G06F5/12 , G06F2205/061 , H03L7/081 , H03L7/087 , H04J3/047 , H04J3/062 , H04J3/0685
摘要： A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
摘要翻译：提供了一种双循环（PLL / DLL）数据同步系统和方法，用于同步系统。特别地，提供了一种使用粒度FIFO填充水平指示符的双循环数据同步的系统和方法。双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环（PLL）和延迟锁环（DLL）。双循环串行器锁定到DLL的输入，它表示FIFO的填充级别。该DLL的粒状FIFO填充电平指示器为移相器提供输入以相应地调整PLL的频率。因此，可以控制数据输入速率的频率，并且可以保持FIFO的恒定填充电平。双环重定时器包括双回路串行器（PLL / DLL）和时钟恢复DLL。重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。

10. 发明授权

US07039825B2 Clock reproducing method and receiving clock producing apparatus allowing for absorption of transmission channel jitter 失效
标题翻译：时钟再现方法和允许吸收传输信道抖动的接收时钟产生装置
公开(公告)号：US07039825B2
公开(公告)日：2006-05-02
申请号：US10164311
申请日：2002-06-07
申请人： Jun Furukawa , Yoshiaki Nozawa , Yasuhiro Arasawa
发明人： Jun Furukawa , Yoshiaki Nozawa , Yasuhiro Arasawa
IPC分类号： G06F1/04
CPC分类号： G06F5/12 , G06F2205/061 , H04N21/4305 , H04N21/64307
摘要： In a receiving clock reproducing method, an estimated value of delay time fluctuation of a received signal is estimated at intervals defined by transmitting clock included in the received signal. To estimate the estimated value, an oscillator counter counts pulses of a reference clock supplied from an independent oscillator while a reading counter counts pulses of the receiving clock. The estimated value is used to control a voltage controlled oscillator for producing the receiving clock.
摘要翻译：在接收时钟再现方法中，以包括在接收信号中的发送时钟定义的间隔估计接收信号的延迟时间波动的估计值。为了估计估计值，振荡器计数器计数从独立振荡器提供的参考时钟的脉冲，而读取计数器计数接收时钟的脉冲。估计值用于控制用于产生接收时钟的压控振荡器。

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