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1. 发明授权

US07098685B1 Scalable serializer-deserializer architecture and programmable interface 有权
标题翻译：可扩展串行器 - 解串器架构和可编程接口
公开(公告)号：US07098685B1
公开(公告)日：2006-08-29
申请号：US10619645
申请日：2003-07-14
申请人： Om P. Agrawal , Bai Nguyen , Kuang Chi , Brad Sharpe-Geisler , Giap Tran
发明人： Om P. Agrawal , Bai Nguyen , Kuang Chi , Brad Sharpe-Geisler , Giap Tran
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/00 , H01L25/00
CPC分类号： H03K19/17744 , H03M9/00
摘要： Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery circuit. The programmable interface further includes programmable input/output buffers and embedded memory to allow the programmable logic device to support a wide range of input/output interface standards.
摘要翻译：公开了提供可编程逻辑器件的可编程输入/输出功能的系统和方法。例如，根据本发明的一个实施例，可编程接口选择性地采用可伸缩串行器 - 解串器和时钟和数据恢复电路。可编程接口还包括可编程输入/输出缓冲器和嵌入式存储器，以允许可编程逻辑器件支持大范围的输入/输出接口标准。

2. 发明授权

US07208975B1 SERDES with programmable I/O architecture 有权
标题翻译： SERDES具有可编程I / O架构
公开(公告)号：US07208975B1
公开(公告)日：2007-04-24
申请号：US11040772
申请日：2005-01-20
申请人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
发明人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.
摘要翻译：在一个实施例中，可编程互连包括专用于传送高速数据的SERDES电路和专用于传送低速数据的输入/输出（I / O）电路。布线结构可配置为将SERDES电路耦合到另一个SERDES电路，到I / O电路的SERDES电路，到SERDES电路的I / O电路以及通过路由路径到另一个I / O电路的I / O电路具有确定性的路由延迟。在另一个实施例中，路由结构包括用于向SERDES电路传送高速数据和从SERDES电路传送高速数据的高速路由结构以及用于向I / O电路传送低速数据的低速路由结构。

3. 发明授权

US06861868B1 High speed interface for a programmable interconnect circuit 有权
标题翻译：用于可编程互连电路的高速接口
公开(公告)号：US06861868B1
公开(公告)日：2005-03-01
申请号：US10463781
申请日：2003-06-16
申请人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
发明人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
IPC分类号： H01L21/82 , H03K19/177 , H03K19/173
CPC分类号： H03K19/17744
摘要： A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.
摘要翻译：包括布置成块的多个I / O电路的可编程半导体器件包括用于每个块的路由结构，其中每个路由结构可以在其块的I / O电路与剩余块内的I / O电路之间编程地路由信号。每个I / O电路与引脚相关联，使得每个块具有一组引脚。 SERDES和FIFO缓冲区与每个块相关联。每个块的SERDES耦合在块的I / O电路和块的引脚组之间。每个FIFO缓冲器耦合在SERDES和其块的I / O电路之间。

4. 发明授权

US06661254B1 Programmable interconnect circuit with a phase-locked loop 有权
标题翻译：具有锁相环的可编程互连电路
公开(公告)号：US06661254B1
公开(公告)日：2003-12-09
申请号：US10021873
申请日：2001-12-14
申请人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
发明人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744 , H03L7/07 , H03L7/081 , H03L7/18
摘要： A programmable interconnect circuit includes a phase-locked loop configured to provide an internal clock signal to I/O cells in the programmable interconnect circuit such that registers in the I/O cells may all be clocked in phase. In addition, the phase-locked loop may provide an external clock signal to the programmable interconnect circuit's routing structure such that external devices may clocked in phase with the external clock signal.
摘要翻译：可编程互连电路包括被配置为向可编程互连电路中的I / O单元提供内部时钟信号的锁相环，使得I / O单元中的寄存器都可以同相计时。此外，锁相环可以向可编程互连电路的路由结构提供外部时钟信号，使得外部设备可以与外部时钟信号同相计时。

5. 发明授权

US07327160B1 SERDES with programmable I/O architecture 有权
标题翻译： SERDES具有可编程I / O架构
公开(公告)号：US07327160B1
公开(公告)日：2008-02-05
申请号：US11676196
申请日：2007-02-16
申请人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
发明人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.
摘要翻译：在本发明的一个实施例中，可编程集成电路包括多个SERDES电路; 多个输入/输出（I / O）电路; 以及可配置为通过具有确定性路由延迟的路由路径提供一个或多个以下连接的路由结构：将SERDES电路耦合到另一个SERDES电路; 将SERDES电路耦合到I / O电路; 将I / O电路耦合到SERDES电路; 并将I / O电路耦合到另一个I / O电路。

6. 发明授权

US06650141B2 High speed interface for a programmable interconnect circuit 有权
标题翻译：用于可编程互连电路的高速接口
公开(公告)号：US06650141B2
公开(公告)日：2003-11-18
申请号：US10023226
申请日：2001-12-14
申请人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
发明人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
IPC分类号： H03K19177
CPC分类号： H03K19/17744
摘要： A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.
摘要翻译：包括布置成块的多个I / O电路的可编程半导体器件包括用于每个块的路由结构，其中每个路由结构可以在其块的I / O电路与剩余块内的I / O电路之间编程地路由信号。每个I / O电路与引脚相关联，使得每个块具有一组引脚。 SERDES和FIFO缓冲区与每个块相关联。每个块的SERDES耦合在块的I / O电路和块的引脚组之间。每个FIFO缓冲器耦合在SERDES和其块的I / O电路之间。

7. 发明授权

US06999543B1 Clock data recovery deserializer with programmable SYNC detect logic 有权
标题翻译：具有可编程SYNC检测逻辑的时钟数据恢复解串器
公开(公告)号：US06999543B1
公开(公告)日：2006-02-14
申请号：US10006610
申请日：2001-12-03
申请人： Jayson Trinh , Chienkuang Chen , Kuang Chi , Mark Becker
发明人： Jayson Trinh , Chienkuang Chen , Kuang Chi , Mark Becker
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H03K5/135 , H03L7/0814 , H03L7/095
摘要： In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted. The SYNC detect logic includes a plurality of reloadable register portions for storing a plurality of synchronization bit patterns for a plurality of communications protocol. Each of a plurality of bit pattern comparators inputs an intermediate parallel data output (IPDO) from the shift register with each cycle of the recovered clock signal and compares for every cycle of the recovered clock signal the shifted recovered serial data bits to each of the synchronization bit patterns. A multiplexer selects one of the outputs of the bit pattern comparators as the VRS signal depending on the communications protocol of the recovered serial data bits.
摘要翻译：在CDR（时钟数据恢复）解串器中，时钟分频器接收恢复的时钟信号（SCLK）并产生分频时钟信号（RPCLK）。分频时钟信号的频率降低，分频时钟信号的每个周期针对恢复的时钟信号的每个计数周期生成直到预定的比例数。串行到并行移位寄存器在恢复的串行数据位中移位恢复的时钟信号的每个周期，并且在划分的时钟信号的每个周期的预定转换处输出移位的恢复串行数据位的预定比例数。 SYNC（同步）检测逻辑断言耦合到时钟分频器的VRS（diVider ReSet）信号，用于控制时钟分频器，以在断言VRS信号时产生分频时钟信号周期的预定转换。 SYNC检测逻辑包括多个可重新加载的寄存器部分，用于存储用于多个通信协议的多个同步位模式。多个比特模式比较器中的每一个比较器从移位寄存器输入中间并行数据输出（IPDO）与恢复的时钟信号的每个周期，并将恢复的时钟信号的每个周期进行比较，将移位的恢复的串行数据比特与每个同步位模式。复用器根据恢复的串行数据位的通信协议，选择位模式比较器的输出之一作为VRS信号。

8. 发明授权

US06993108B1 Digital phase locked loop with programmable digital filter 有权
标题翻译：带可编程数字滤波器的数字锁相环
公开(公告)号：US06993108B1
公开(公告)日：2006-01-31
申请号：US10006516
申请日：2001-12-03
申请人： Kuang Chi , Ling Wang , Antony Davies
发明人： Kuang Chi , Ling Wang , Antony Davies
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/089 , H03L7/093 , H04J3/0605 , H04L7/0025 , H04L7/0337
摘要： In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth) value programmed into the first reloadable register portion through a first port, and a second reloadable register portion stores a DBW (differential bandwidth) value programmed into the second reloadable register portion through a second port. An up—counter generates an UP—CNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal. A down—counter generates a DOWN—CNT value by counting up each DOWN signal pulse generated by the phase transition detector when the first phase of the SDIN (serial data input) signal lags the second phase of the current ACLK (recovered clock) signal. One of a FWD (forward) signal or a BWD (backward) signal are asserted or are both not asserted depending on the UP—CNT value and the DN—CNT value in comparison to the TBW value and the DBW value. Another clock signal having a leading phase from the current ACLK signal is selected as a new ACLK (recovered clock) signal when the FWD signal is asserted. Or, another clock signal having a lagging phase from the current ACLK signal is selected as the new ACLK (recovered clock) signal when the BWD signal is asserted. Or, the current ACLK signal remains as the new ACLK (recovered clock) signal if neither the FWD signal nor the BWD signal is asserted.
摘要翻译：在用于最小化多个通信协议的误码率的DPLL（数字锁相环）的数字滤波器中，第一可重新加载的寄存器部分通过第一端口将经编程的TBW（总带宽）值存储到第一可重新加载的寄存器部分中，以及第二可重新加载的寄存器部分通过第二端口存储编程到第二可重新加载的寄存器部分中的DBW（差分带宽）值。通过在SDIN（串行数据输入）信号的第一相位上递增由相变检测器产生的每个UP信号脉冲，上计数器 - 计数器产生UP CNT值导致当前ACLK（恢复时钟）信号的第二阶段。计数器通过在SDIN（串行数据输入）信号的第一相位上递增由相变检测器产生的每个DOWN信号脉冲，产生一个DOWN 滞后于当前ACLK（恢复时钟）信号的第二阶段。 FWD（正向）信号或BWD（反向）信号中的一个被断言或者两者都不被断言，这取决于CNT的值和DN < - > CNT值与TBW值和DBW值进行比较。当FWD信号被断言时，具有来自当前ACLK信号的引导相位的另一时钟信号被选择为新的ACLK（恢复时钟）信号。或者，当BWD信号有效时，选择具有来自当前ACLK信号的滞后相位的另一时钟信号作为新的ACLK（恢复时钟）信号。或者，如果FWD信号和BWD信号都不被断言，则当前的ACLK信号保持为新的ACLK（恢复时钟）信号。

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