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1. 发明授权

US06999543B1 Clock data recovery deserializer with programmable SYNC detect logic 有权
标题翻译：具有可编程SYNC检测逻辑的时钟数据恢复解串器
公开(公告)号：US06999543B1
公开(公告)日：2006-02-14
申请号：US10006610
申请日：2001-12-03
申请人： Jayson Trinh , Chienkuang Chen , Kuang Chi , Mark Becker
发明人： Jayson Trinh , Chienkuang Chen , Kuang Chi , Mark Becker
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H03K5/135 , H03L7/0814 , H03L7/095
摘要： In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted. The SYNC detect logic includes a plurality of reloadable register portions for storing a plurality of synchronization bit patterns for a plurality of communications protocol. Each of a plurality of bit pattern comparators inputs an intermediate parallel data output (IPDO) from the shift register with each cycle of the recovered clock signal and compares for every cycle of the recovered clock signal the shifted recovered serial data bits to each of the synchronization bit patterns. A multiplexer selects one of the outputs of the bit pattern comparators as the VRS signal depending on the communications protocol of the recovered serial data bits.
摘要翻译：在CDR（时钟数据恢复）解串器中，时钟分频器接收恢复的时钟信号（SCLK）并产生分频时钟信号（RPCLK）。分频时钟信号的频率降低，分频时钟信号的每个周期针对恢复的时钟信号的每个计数周期生成直到预定的比例数。串行到并行移位寄存器在恢复的串行数据位中移位恢复的时钟信号的每个周期，并且在划分的时钟信号的每个周期的预定转换处输出移位的恢复串行数据位的预定比例数。 SYNC（同步）检测逻辑断言耦合到时钟分频器的VRS（diVider ReSet）信号，用于控制时钟分频器，以在断言VRS信号时产生分频时钟信号周期的预定转换。 SYNC检测逻辑包括多个可重新加载的寄存器部分，用于存储用于多个通信协议的多个同步位模式。多个比特模式比较器中的每一个比较器从移位寄存器输入中间并行数据输出（IPDO）与恢复的时钟信号的每个周期，并将恢复的时钟信号的每个周期进行比较，将移位的恢复的串行数据比特与每个同步位模式。复用器根据恢复的串行数据位的通信协议，选择位模式比较器的输出之一作为VRS信号。

2. 发明授权

US5706227A Double poly split gate PMOS flash memory cell 失效
标题翻译：双重多分支栅极PMOS闪存单元
公开(公告)号：US5706227A
公开(公告)日：1998-01-06
申请号：US568544
申请日：1995-12-07
申请人： Shang-De Ted Chang , Jayson Trinh
发明人： Shang-De Ted Chang , Jayson Trinh
IPC分类号： G11C16/04 , H01L27/115 , H01L29/423 , H01L29/788 , G11C11/34 , G11C7/00
CPC分类号： H01L29/7885 , G11C16/0425 , H01L27/115 , H01L29/42324
摘要： A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin tunnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying select and control gate is insulated from the floating gate by an insulating layer. The select and control gate including an elongated extension portion for preventing overprogramming of the circuit. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.
摘要翻译： P沟道MOS存储单元具有形成在N阱中的P +源极和漏极区。在井表面和上浮动门之间提供薄隧道氧化物。在一个实施例中，薄隧道氧化物在有源区域和器件的大部分上延伸。上覆的选择和控制栅极通过绝缘层与浮动栅极绝缘。选择和控制门包括用于防止电路过度编程的细长延伸部分。通过从通道区域的漏极端到浮动栅极的热电子注入来对器件进行编程，而不会产生雪崩击穿，从而允许在编程期间对单元进行位选择。通过从浮置栅极到N阱的电子隧穿实现擦除，源极，漏极和N阱区域均匀偏置。由于没有高的漏/阱结偏置电压，可以减少电池的通道长度，而不会产生和破坏性结应力。

3. 发明授权

US5691939A Triple poly PMOS flash memory cell 失效
标题翻译：三重多晶硅快闪存储单元
公开(公告)号：US5691939A
公开(公告)日：1997-11-25
申请号：US568835
申请日：1995-12-07
申请人： Shang-De Ted Chang , Jayson Trinh
发明人： Shang-De Ted Chang , Jayson Trinh
IPC分类号： G11C16/04 , H01L27/115 , H01L29/423 , H01L29/788 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0425 , H01L29/42328 , H01L29/7885
摘要： A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin runnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying control gate is insulated from the floating gate by a first insulating layer. An overlying select gate is insulated from the control gate by an insulating layer. The select gate includes an elongated extension portion for preventing overprogramming of the circuit. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring any destructive junction stress.
摘要翻译： P沟道MOS存储单元具有形成在N阱中的P +源极和漏极区。在井表面和覆盖的浮动浇口之间设置有薄的氧化层。在一个实施例中，薄隧道氧化物在有源区域和器件的大部分上延伸。上覆的控制栅极通过第一绝缘层与浮动栅极绝缘。上覆选择栅极通过绝缘层与控制栅极绝缘。选择门包括用于防止电路过度编程的细长延伸部分。通过从通道区域的漏极端到浮动栅极的热电子注入来对器件进行编程，而不会产生雪崩击穿，从而允许在编程期间对单元进行位选择。通过从浮置栅极到N阱的电子隧穿实现擦除，源极，漏极和N阱区域均匀偏置。由于没有高的漏/阱结偏置电压，可以减小电池的通道长度，而不会产生任何破坏性结应力。

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