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1. 发明授权

US07208975B1 SERDES with programmable I/O architecture 有权
标题翻译： SERDES具有可编程I / O架构
公开(公告)号：US07208975B1
公开(公告)日：2007-04-24
申请号：US11040772
申请日：2005-01-20
申请人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
发明人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.
摘要翻译：在一个实施例中，可编程互连包括专用于传送高速数据的SERDES电路和专用于传送低速数据的输入/输出（I / O）电路。布线结构可配置为将SERDES电路耦合到另一个SERDES电路，到I / O电路的SERDES电路，到SERDES电路的I / O电路以及通过路由路径到另一个I / O电路的I / O电路具有确定性的路由延迟。在另一个实施例中，路由结构包括用于向SERDES电路传送高速数据和从SERDES电路传送高速数据的高速路由结构以及用于向I / O电路传送低速数据的低速路由结构。

2. 发明授权

US07327160B1 SERDES with programmable I/O architecture 有权
标题翻译： SERDES具有可编程I / O架构
公开(公告)号：US07327160B1
公开(公告)日：2008-02-05
申请号：US11676196
申请日：2007-02-16
申请人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
发明人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.
摘要翻译：在本发明的一个实施例中，可编程集成电路包括多个SERDES电路; 多个输入/输出（I / O）电路; 以及可配置为通过具有确定性路由延迟的路由路径提供一个或多个以下连接的路由结构：将SERDES电路耦合到另一个SERDES电路; 将SERDES电路耦合到I / O电路; 将I / O电路耦合到SERDES电路; 并将I / O电路耦合到另一个I / O电路。

3. 发明授权

US5598346A Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks 失效
标题翻译：可配置逻辑块的阵列，包括用于向不同的多个逻辑块广播时钟信号的网络装置
公开(公告)号：US5598346A
公开(公告)日：1997-01-28
申请号：US596679
申请日：1996-02-05
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes an internal clock selector for selecting a CLB-internal clock and at least one register that is responsive to the selected CLB-internal clock. The configurable interconnect network includes clock-carrying longlines extending in different directions past each CLB for broadcasting clock signals. The broadcast clock signals can originate outside the programmable integrated circuit or such broadcast clock signals can be generated within one or more of the CLB's and thereafter broadcast by way of the clock broadcasting longlines to others of the CLB's.
摘要翻译：可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。每个CLB包括用于选择CLB内部时钟的内部时钟选择器和响应于所选CLB内部时钟的至少一个寄存器。可配置互连网络包括延伸穿过每个CLB的不同方向的时钟传送延长线，用于广播时钟信号。广播时钟信号可以起源于可编程集成电路之外，或者这种广播时钟信号可以在一个或多个CLB内产生，然后通过时钟广播延长线向CLB的其他人广播。

4. 发明授权

US5469368A Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output 失效
标题翻译：每个可配置逻辑块的阵列包括第一查找表输出，耦合以选择性地将第二查找的输出替换为备用功能输出
公开(公告)号：US5469368A
公开(公告)日：1995-11-21
申请号：US462934
申请日：1995-06-05
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a plurality of function lookup tables (LUT's) each defined by a bit storage area and a select means responsive to input signals for selecting a stored bit. The design includes first and second LUT's where the first LUT output determines whether the output of the second LUT will be forwarded or replaced by another function output.
摘要翻译：可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。每个CLB包括由比特存储区域定义的多个功能查找表（LUT）和响应于用于选择存储的比特的输入信号的选择装置。该设计包括第一和第二LUT，其中第一LUT输出确定第二LUT的输出是否将被另一个功能输出转发或替换。

5. 发明授权

US5212652A Programmable gate array with improved interconnect structure 失效
标题翻译：可编程门阵列与改进的互连结构
公开(公告)号：US5212652A
公开(公告)日：1993-05-18
申请号：US394221
申请日：1989-08-15
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of contact signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

6. 发明授权

US06828823B1 Non-volatile and reconfigurable programmable logic devices 有权
标题翻译：非易失性和可重新配置的可编程逻辑器件
公开(公告)号：US06828823B1
公开(公告)日：2004-12-07
申请号：US10439602
申请日：2003-05-16
申请人： Cyrus Tsui , Benny Ma , Om P. Agrawal , Ju Shen , Sam Tsai , Jack Wong , Chan-Chi Jason Cheng
发明人： Cyrus Tsui , Benny Ma , Om P. Agrawal , Ju Shen , Sam Tsai , Jack Wong , Chan-Chi Jason Cheng
IPC分类号： H03K19177
CPC分类号： H03K19/17752 , H03K19/1776 , H03K19/17768
摘要： An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.
摘要翻译：集成电路包括非易失性和易失性存储器，易失性存储器控制集成电路的功能。公开了用于通过一个或多个数据端口对不同类型的存储器进行编程以提供系统内可编程性和动态可重构性的各种技术。如果来自非易失性存储器的数据直接传输到易失性存储器，则不需要外部配置设备。

7. 发明授权

US5586044A Array of configurable logic blocks including cascadable lookup tables 失效
标题翻译：可配置逻辑块的数组，包括级联查找表
公开(公告)号：US5586044A
公开(公告)日：1996-12-17
申请号：US461196
申请日：1995-06-05
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a plurality of function lookup tables (LUT's) each defined by a bit storage area and a select means responsive to input signals for selecting a stored bit. The design includes first and second LUT's that share a same plurality of input signals where the output of one of the LUT's is connectable by direct connect means to an input of a further pair of LUT's.
摘要翻译：可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。每个CLB包括由比特存储区域定义的多个功能查找表（LUT）和响应于用于选择存储的比特的输入信号的选择装置。该设计包括共享相同多个输入信号的第一和第二LUT，其中一个LUT的输出可以通过直接连接装置连接到另一对LUT的输入。

8. 发明授权

US5422823A Programmable gate array device having cascaded means for function definition 失效
标题翻译：具有用于功能定义的级联装置的可编程门阵列器件
公开(公告)号：US5422823A
公开(公告)日：1995-06-06
申请号：US271872
申请日：1994-07-07
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.
摘要翻译：具有改进的互连结构的可编程门阵列有助于多源网络，跨阵列的信号长距离通信以及在对称互连结构中的网络的创建。互连包括将阵列中的每个可配置逻辑块的直接连接到八个邻居，包括相邻的可配置逻辑块和下一个相邻的可配置逻辑块。此外，互连包括由可配置逻辑块的输出驱动但未通过互连提交到任何特定逻辑块的输入的未提交的长线。相反，未提交的长行致力于连接到互连的其他段。互连结构还包括在互连中的水平和垂直总线的交叉处的交错矩阵。可以在两个方向上配置的缓冲区的重新加载与互连中的双向线路相关联，并包括旁路路径。互连提供了来自芯片外的控制信号，阵列中的任何可配置逻辑块以及阵列中的输入/输出结构与阵列中的任何或所有其他可配置逻辑块和输入/输出块的通信。

9. 发明授权

US5587921A Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer 失效
标题翻译：每个可配置逻辑块的阵列包括具有耦合到第一多路复用器并且具有耦合到第二多路复用器的输出的输入的查找表
公开(公告)号：US5587921A
公开(公告)日：1996-12-24
申请号：US560933
申请日：1995-11-20
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a lookup table having inputs and outputs, a first multiplexer means for applying a selected subset of CLB input signals to the lookup table inputs, and a second multiplexer means for routing lookup table output signals to selectable destinations. The first multiplexer means can programmably route input signals to the lookup table inputs from a variety of sources including first through fourth direct-connect receiving terminals distributed symmetrically about the CLB, first through fourth longline receiving terminals distributed symmetrically about the CLB, first through fourth general-interconnect receiving terminals distributed symmetrically about the CLB, and first through fourth feedback means distributed symmetrically within the CLB. The second multiplexer means can programmably route output signals from the lookup table to first through fourth output macrocells distributed symmetrically about the CLB. The first through fourth output macrocells can respectively couple the routed signals to first through fourth direct-connect outputting terminals distributed symmetrically about the CLB, first through fourth tristate outputting terminals distributed symmetrically about the CLB, and the first through fourth feedback means.
摘要翻译：可编程集成电路包括可配置逻辑块（CLB），可配置输入/输出块（IOB）和可配置互连网络，用于在CLB和IOB之间提供程序定义的信号路由。每个CLB包括具有输入和输出的查找表，用于将选定的CLB输入信号的子集应用于查找表输入的第一多路复用器装置和用于将查找表输出信号路由到可选目的地的第二多路复用器装置。第一多路复用器装置可编程地将输入信号路由到各种源的查找表输入，包括关于CLB对称分布的第一至第四直接接收终端，关于CLB对称分布的第一至第四延长线接收终端，第一至第四通用 - 关于CLB对称分布的接收端子以及在CLB内对称分布的第一至第四反馈装置。第二多路复用器装置可编程地将来自查找表的输出信号路由到关于CLB对称分布的第一到第四输出宏小区。第一到第四输出宏单元可以分别将路由信号耦合到关于CLB对称地分布的第一到第四直接连接输出端子，关于CLB对称地分布的第一到第四三态输出端子以及第一到第四反馈装置。

10. 发明授权

US5359536A Programmable gate array with improved interconnect structure, input/output structure and configurable logic block 失效
公开(公告)号：US5359536A
公开(公告)日：1994-10-25
申请号：US25551
申请日：1993-03-03
申请人： Om P. Agrawal , Michael J. Wright , Ju Shen
发明人： Om P. Agrawal , Michael J. Wright , Ju Shen
IPC分类号： G06F7/00 , G06F7/575 , G06F17/50 , H03K17/693 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17732 , H03K19/17744
摘要： A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path. The interconnect provides for communication of control signals from off the chip, from any configurable logic block in the array, and from the input/output structures in the array to any or all other configurable logic blocks and input/output blocks in the array.

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