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1. 发明申请

US20180241541A1 METHOD AND CIRCUITS FOR PHASE-LOCKED LOOPS 审中-公开
公开(公告)号：US20180241541A1
公开(公告)日：2018-08-23
申请号：US15896319
申请日：2018-02-14
申请人： Analog Bits Inc.
发明人： Alan C. Rogers , Kowshik Murali , Raghunand Bhagwan
IPC分类号： H04L7/033 , H03L7/093 , H03L7/089 , H03L7/091
CPC分类号： H04L7/033 , H03L7/089 , H03L7/0891 , H03L7/091 , H03L7/093 , H04L7/0008
摘要： A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.

2. 发明申请

US20180109265A1 Differential Phase-Frequency Detector 审中-公开
公开(公告)号：US20180109265A1
公开(公告)日：2018-04-19
申请号：US15843575
申请日：2017-12-15
申请人： International Business Machines Corporation
发明人： David M. Friend , Grant P. Kesselring , James D. Strom , Alan P. Wagstaff
IPC分类号： H03L7/085 , H03L7/089
CPC分类号： H03L7/085 , H03L7/089
摘要： A phase-frequency detector (PFD) is electrically coupled to a charge pump of a phase-locked-loop (PLL). The PFD includes a first differential latch electrically coupled to the charge pump. The first differential latch drives a differential pair of increment signals to the charge pump in response to differential pairs of both reference clock signals and reset signals. The PFD also includes a second differential latch electrically coupled to the charge pump. The second differential latch drives a differential pair of decrement signals to the charge pump in response to differential pairs of both feedback clock signals and reset signals. The PFD also includes a differential AND gate electrically coupled to both the first differential latch and the second differential latch. The differential AND gate drives the differential pair of reset signals to both of the differential latches in response to the differential pairs of both increment signals and decrement signals.

3. 发明申请

US20180107239A1 CLOCK FOR RECORDING DEVICES 审中-公开
公开(公告)号：US20180107239A1
公开(公告)日：2018-04-19
申请号：US15729782
申请日：2017-10-11
申请人： SOUND DEVICES, LLC
发明人： Matt Anderson , Francois Morin
IPC分类号： G06F1/04 , H03L7/099 , H03L7/089 , H03J7/06 , H04L7/00 , H03L7/093
CPC分类号： G06F1/04 , G04G3/00 , G06F1/12 , H03J7/065 , H03L7/089 , H03L7/093 , H03L7/0992 , H03L7/16 , H04L7/0004 , H04Q9/00
摘要： A method includes receiving, by a recording device, an indication of an initializing time and receiving, by the recording device, an indication of a timing pace. The method also includes maintaining, by the recording device, an updated current time based on the initializing time and the timing pace and sensing, via a sensor of the recording device, a condition. The method further includes storing, in memory of the recording device, an indication of the condition and an associated indication of the updated current time. The indication of the updated current time corresponds to when the condition was sensed by the sensor.

4. 发明申请

US20180097513A1 CIRCUIT AND METHOD TO GENERATE FREQUENCY PROPORTIONAL CURRENT 有权
公开(公告)号：US20180097513A1
公开(公告)日：2018-04-05
申请号：US15282957
申请日：2016-09-30
申请人： Texas Instruments Deutschland GmbH
发明人： Michael Couleur , Neil Gibson , Antonio Priego
IPC分类号： H03K7/06 , H02M3/07 , H03K4/52 , H03L7/081
CPC分类号： H03K7/06 , H02M3/07 , H02M3/156 , H02M2001/0006 , H02M2001/0035 , H02M2001/0048 , H03K3/033 , H03L5/02 , H03L7/0812 , H03L7/089
摘要： Disclosed examples include self-biased DLL circuits to generate a bias current signal proportional to a repetition frequency of a first signal representing continuous switching or discontinued switching operation of the DC-DC converter. The DLL circuit includes a monostable multivibrator to provide a pulse output signal in response to an edge of the first signal with a pulse duration set by a control current signal, a phase detector to provide output signals according to a phase difference between an edge of the pulse output signal and the first signal, and an output circuit to provide an output signal according to the phase detector output signals and according to an offset signal, to provide the bias current signal according to the output signal, and to provide the control current signal according to the output signal.

5. 发明申请

US20170302283A1 PHASE DETECTION METHOD BASED ON A PLURALITY OF CONSECUTIVE VALUES OF A RECEIVING SIGNAL 审中-公开
公开(公告)号：US20170302283A1
公开(公告)日：2017-10-19
申请号：US15517451
申请日：2015-10-14
申请人： SONOVUM AG
发明人： MIROSLAW WROBEL , Adam KOLANY
IPC分类号： H03L7/091 , H04L27/233 , G01R19/25 , H03L7/089 , H04L7/033 , H04L12/26
CPC分类号： H03L7/091 , G01R19/25 , H03L7/089 , H04L7/033 , H04L27/2334
摘要： The invention relates to a phase detection method (200), comprising the following steps: receiving a plurality of consecutive values of a receiving signal (Y) with a known sampling frequency fs as a reaction to a transmitting signal having a known transmitting frequency fw; determining two differential values (ΔY1, ΔY2), each coming from two consecutive values out of three consecutive values (Y1, Y2, Y3) of the receiving signal (Y); and determining a phase real part (U) and a phase imaginary part (V) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V) and the two differential values (ΔY1, ΔY2).

6. 发明授权

US09705513B2 Frequency source with improved phase noise 有权
公开(公告)号：US09705513B2
公开(公告)日：2017-07-11
申请号：US14560824
申请日：2014-12-04
申请人： RAYTHEON COMPANY
发明人： Matthew A. Morton , Tina P. Srivastava
IPC分类号： H03L7/093 , H03H7/06 , H03L7/089
CPC分类号： H03L7/093 , H03H7/06 , H03L7/089
摘要： A frequency source with improved phase noise. In one embodiment a phase-locked loop is used as a component of a frequency source and a signal to noise enhancer (SNE) is used to suppress phase noise produced by the phase-locked loop. The signal to noise enhancer is a nonlinear passive device that attenuates low-power signals while transmitting high power signals with little loss. The signal to noise enhancer may be fabricated as a thin film of yttrium iron garnet (YIG) epitaxially grown on a gadolinium gallium garnet (GGG) substrate, the GGG substrate being secured to a microwave transmission line from the input to the output of the signal to noise enhancer, such that the thin film of yttrium iron garnet is close to the transmission line.

7. 发明授权

US09520883B2 Frequency detection circuit and reception circuit 有权
标题翻译：频率检测电路和接收电路
公开(公告)号：US09520883B2
公开(公告)日：2016-12-13
申请号：US14834927
申请日：2015-08-25
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
IPC分类号： H03L7/06 , H03L7/085 , H03L7/087 , H03L7/089
CPC分类号： H03L7/085 , H03L7/087 , H03L7/089
摘要： A frequency detection circuit includes: a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value; a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value; a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock; a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas; and a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector.
摘要翻译：频率检测电路包括：第一比较电路，被配置为输出通过比较高于第一阈值的第二阈值而产生的第一比较结果; 第二比较电路，被配置为输出比第一阈值低的第三阈值之间的比较产生的第二比较结果; 第三比较电路，被配置为输出在第二时钟的第二定时处的输入数据和第一阈值之间的比较产生的第三比较结果; 相位检测器，被配置为通过将一位宽度时间中的相位除以三个区域来确定输入数据的边缘在哪个区域中的哪个区域中; 以及相位旋转检测器，被配置为基于相位检测器中的检测结果的变化来检测相位的旋转方向。

8. 发明授权

US09520881B1 Systems and methods for tuning an oscillator frequency 有权
标题翻译：用于调谐振荡器频率的系统和方法
公开(公告)号：US09520881B1
公开(公告)日：2016-12-13
申请号：US14927803
申请日：2015-10-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Abhijit Kumar Das , Krishnasawamy Nagaraj , Rahul Bhandarkar
IPC分类号： H03L7/02 , H03K3/0231 , H03K3/011
CPC分类号： H03L7/02 , H03K3/011 , H03K3/0231 , H03L7/089
摘要： A system for tuning an oscillator frequency. The system includes a trimmed calibration circuit comprising a comparator and trimmed delay element and calibration logic. The calibration logic is configured to receive an output of the comparator and control an on time and an off time of an oscillator based on the output of the comparator.
摘要翻译：用于调谐振荡器频率的系统。该系统包括修整的校准电路，其包括比较器和修整的延迟元件和校准逻辑。校准逻辑被配置为接收比较器的输出，并且基于比较器的输出来控制振荡器的接通时间和关断时间。

9. 发明授权

US09503105B2 Phase frequency detector (PFD) circuit with improved lock time 有权
标题翻译：相位频率检测器（PFD）电路具有改进的锁定时间
公开(公告)号：US09503105B2
公开(公告)日：2016-11-22
申请号：US14868785
申请日：2015-09-29
申请人： Texas Instruments Incorporated
发明人： Peeyoosh Nitin Mirajkar , Jagdish Chand Goyal , Sankaran Aniruddhan
IPC分类号： H03L7/06 , H03L7/095 , H03L7/089 , H03L7/107
CPC分类号： H03L7/095 , H03L7/089 , H03L7/1072 , H03L7/1077
摘要： Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.
摘要翻译：所描述的示例包括控制锁相环（PLL）或其他锁定电路的锁定时间的电路和方法，其中相位频率检测器（PFD）电路从第一模式切换以向电荷泵提供控制输入信号作为脉冲信号具有对应于参考时钟信号和反馈时钟信号之间的相位差的脉冲宽度到第二模式，以响应于检测到的周期滑移条件将控制输入信号保持在恒定值一段预定时间以增强环路在频率转换期间过滤电流，以减少锁定电路的锁定时间。

10. 发明授权

US09496916B2 Semiconductor device, receiver, transmitter, transceiver and communication system 有权
标题翻译：半导体器件，接收器，发射器，收发器和通信系统
公开(公告)号：US09496916B2
公开(公告)日：2016-11-15
申请号：US14332657
申请日：2014-07-16
申请人： Renesas Electronics Corporation
发明人： Masao Nakadaira
IPC分类号： H04B1/7073 , H03L7/085 , H04B1/02 , H04B1/06 , H04B1/38 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/091
CPC分类号： H04B1/7073 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/085 , H03L7/089 , H03L7/091 , H04B1/02 , H04B1/06 , H04B1/38
摘要： A semiconductor device, includes a clock and data recovery unit to which a receive signal is inputted and which extracts, based on an operation clock signal, a clock signal and a data signal from the receive signal, a frequency error adjusting unit which generates a frequency error signal indicating a frequency error between the clock signal extracted from the receive signal and the operation clock signal, an operation clock generation unit which controls, based on the frequency error signal, a frequency of the operation clock signal, and a Spread Spectrum Clock Generator (SSCG) unit which varies the frequency of the operation clock signal by the SSCG unit based on the frequency error signal.
摘要翻译：一种半导体器件，包括：时钟和数据恢复单元，接收信号输入到该时钟和数据恢复单元，其基于操作时钟信号从接收信号中提取时钟信号和数据信号;频率误差调整单元，其产生频率误差信号，指示从接收信号提取的时钟信号与操作时钟信号之间的频率误差;操作时钟产生单元，其基于频率误差信号控制操作时钟信号的频率;以及扩频时钟发生器（SSCG）单元，其基于频率误差信号改变SSCG单元的操作时钟信号的频率。

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