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1. 发明申请

US20210099175A1 Method and System for Providing a Configurable Logic Device Having a Programmable DSP Block 有权
公开(公告)号：US20210099175A1
公开(公告)日：2021-04-01
申请号：US16586891
申请日：2019-09-27
申请人： Jianhua Liu , Chienkuang Chen
发明人： Jianhua Liu , Chienkuang Chen
IPC分类号： H03K19/177
摘要： A programmable logic device (“PLD”) contains programmable digital signal processing (“DSP”) blocks operable to be selectively programmed to perform one or more logic functions. The PLD, in one embodiment, includes configurable logic blocks (“LBs”), an input and output (“I/O”) block, and programmable DSP blocks. The configurable LBs are able to be selectively programmed to perform one or more logic functions. The I/O block includes I/O ports for facilitating data transfer. The programmable DSP blocks are configured to perform various predefined logic functions. Each of the programmable DSP blocks, in one aspect, includes at least one configurable DSP which, in one embodiment, includes a 27×18 multiplier and a 12×12 multiplier.

2. 发明授权

US06661254B1 Programmable interconnect circuit with a phase-locked loop 有权
标题翻译：具有锁相环的可编程互连电路
公开(公告)号：US06661254B1
公开(公告)日：2003-12-09
申请号：US10021873
申请日：2001-12-14
申请人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
发明人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
IPC分类号： H01L2500
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744 , H03L7/07 , H03L7/081 , H03L7/18
摘要： A programmable interconnect circuit includes a phase-locked loop configured to provide an internal clock signal to I/O cells in the programmable interconnect circuit such that registers in the I/O cells may all be clocked in phase. In addition, the phase-locked loop may provide an external clock signal to the programmable interconnect circuit's routing structure such that external devices may clocked in phase with the external clock signal.
摘要翻译：可编程互连电路包括被配置为向可编程互连电路中的I / O单元提供内部时钟信号的锁相环，使得I / O单元中的寄存器都可以同相计时。此外，锁相环可以向可编程互连电路的路由结构提供外部时钟信号，使得外部设备可以与外部时钟信号同相计时。

3. 发明授权

US07003066B1 Digital phase locked loop with phase selector having minimized number of phase interpolators 有权
标题翻译：具有相位选择器的数字锁相环具有最小数量的相位内插器
公开(公告)号：US07003066B1
公开(公告)日：2006-02-21
申请号：US10006559
申请日：2001-12-03
申请人： Antony Davies , Chienkuang Chen , Ling Wang
发明人： Antony Davies , Chienkuang Chen , Ling Wang
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/095 , H04L7/0337
摘要： In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.
摘要翻译：在本发明的一个实施例中，相位选择单元用于产生恢复的时钟信号（SCLK），相位选择信号发生器响应于来自数字滤波器的FWD信号和BWD信号产生相位选择信号。如果SDIN（串行数字输入）信号的相位导致恢复的时钟信号的相位，则数字滤波器置位FWD信号，并且如果SDIN（串行数字输入）信号的相位滞后于相位，则断言BWD信号恢复时钟信号。多路复用器接收以预定相位顺序排列的多个给定时钟信号，并输出所选择的第一和第二输出时钟信号，每一个是给定的时钟信号之一。相位插值器从多路复用器接收所选择的第一和第二输出时钟信号，以产生具有在第一和第二输出时钟信号的相位之间被相位插值的相位的恢复时钟信号。

4. 发明授权

US06650141B2 High speed interface for a programmable interconnect circuit 有权
标题翻译：用于可编程互连电路的高速接口
公开(公告)号：US06650141B2
公开(公告)日：2003-11-18
申请号：US10023226
申请日：2001-12-14
申请人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
发明人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
IPC分类号： H03K19177
CPC分类号： H03K19/17744
摘要： A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.
摘要翻译：包括布置成块的多个I / O电路的可编程半导体器件包括用于每个块的路由结构，其中每个路由结构可以在其块的I / O电路与剩余块内的I / O电路之间编程地路由信号。每个I / O电路与引脚相关联，使得每个块具有一组引脚。 SERDES和FIFO缓冲区与每个块相关联。每个块的SERDES耦合在块的I / O电路和块的引脚组之间。每个FIFO缓冲器耦合在SERDES和其块的I / O电路之间。

5. 发明授权

US11043950B2 Method and system for providing a configurable logic device having a programmable DSP block 有权
公开(公告)号：US11043950B2
公开(公告)日：2021-06-22
申请号：US16586891
申请日：2019-09-27
申请人： Jianhua Liu , Chienkuang Chen
发明人： Jianhua Liu , Chienkuang Chen
IPC分类号： H03K19/17728 , H03K19/17704 , H03K19/17736
摘要： A programmable logic device (“PLD”) contains programmable digital signal processing (“DSP”) blocks operable to be selectively programmed to perform one or more logic functions. The PLD, in one embodiment, includes configurable logic blocks (“LBs”), an input and output (“I/O”) block, and programmable DSP blocks. The configurable LBs are able to be selectively programmed to perform one or more logic functions. The I/O block includes I/O ports for facilitating data transfer. The programmable DSP blocks are configured to perform various predefined logic functions. Each of the programmable DSP blocks, in one aspect, includes at least one configurable DSP which, in one embodiment, includes a 27×18 multiplier and a 12×12 multiplier.

6. 发明授权

US06999543B1 Clock data recovery deserializer with programmable SYNC detect logic 有权
标题翻译：具有可编程SYNC检测逻辑的时钟数据恢复解串器
公开(公告)号：US06999543B1
公开(公告)日：2006-02-14
申请号：US10006610
申请日：2001-12-03
申请人： Jayson Trinh , Chienkuang Chen , Kuang Chi , Mark Becker
发明人： Jayson Trinh , Chienkuang Chen , Kuang Chi , Mark Becker
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H03K5/135 , H03L7/0814 , H03L7/095
摘要： In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted. The SYNC detect logic includes a plurality of reloadable register portions for storing a plurality of synchronization bit patterns for a plurality of communications protocol. Each of a plurality of bit pattern comparators inputs an intermediate parallel data output (IPDO) from the shift register with each cycle of the recovered clock signal and compares for every cycle of the recovered clock signal the shifted recovered serial data bits to each of the synchronization bit patterns. A multiplexer selects one of the outputs of the bit pattern comparators as the VRS signal depending on the communications protocol of the recovered serial data bits.
摘要翻译：在CDR（时钟数据恢复）解串器中，时钟分频器接收恢复的时钟信号（SCLK）并产生分频时钟信号（RPCLK）。分频时钟信号的频率降低，分频时钟信号的每个周期针对恢复的时钟信号的每个计数周期生成直到预定的比例数。串行到并行移位寄存器在恢复的串行数据位中移位恢复的时钟信号的每个周期，并且在划分的时钟信号的每个周期的预定转换处输出移位的恢复串行数据位的预定比例数。 SYNC（同步）检测逻辑断言耦合到时钟分频器的VRS（diVider ReSet）信号，用于控制时钟分频器，以在断言VRS信号时产生分频时钟信号周期的预定转换。 SYNC检测逻辑包括多个可重新加载的寄存器部分，用于存储用于多个通信协议的多个同步位模式。多个比特模式比较器中的每一个比较器从移位寄存器输入中间并行数据输出（IPDO）与恢复的时钟信号的每个周期，并将恢复的时钟信号的每个周期进行比较，将移位的恢复的串行数据比特与每个同步位模式。复用器根据恢复的串行数据位的通信协议，选择位模式比较器的输出之一作为VRS信号。

7. 发明授权

US06861868B1 High speed interface for a programmable interconnect circuit 有权
标题翻译：用于可编程互连电路的高速接口
公开(公告)号：US06861868B1
公开(公告)日：2005-03-01
申请号：US10463781
申请日：2003-06-16
申请人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
发明人： Om P. Agrawal , Jinghui Zhu , Kuang Chi , ChienKuang Chen
IPC分类号： H01L21/82 , H03K19/177 , H03K19/173
CPC分类号： H03K19/17744
摘要： A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.
摘要翻译：包括布置成块的多个I / O电路的可编程半导体器件包括用于每个块的路由结构，其中每个路由结构可以在其块的I / O电路与剩余块内的I / O电路之间编程地路由信号。每个I / O电路与引脚相关联，使得每个块具有一组引脚。 SERDES和FIFO缓冲区与每个块相关联。每个块的SERDES耦合在块的I / O电路和块的引脚组之间。每个FIFO缓冲器耦合在SERDES和其块的I / O电路之间。

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