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1. 发明授权

US07327160B1 SERDES with programmable I/O architecture 有权
标题翻译： SERDES具有可编程I / O架构
公开(公告)号：US07327160B1
公开(公告)日：2008-02-05
申请号：US11676196
申请日：2007-02-16
申请人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
发明人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.
摘要翻译：在本发明的一个实施例中，可编程集成电路包括多个SERDES电路; 多个输入/输出（I / O）电路; 以及可配置为通过具有确定性路由延迟的路由路径提供一个或多个以下连接的路由结构：将SERDES电路耦合到另一个SERDES电路; 将SERDES电路耦合到I / O电路; 将I / O电路耦合到SERDES电路; 并将I / O电路耦合到另一个I / O电路。

2. 发明授权

US07208975B1 SERDES with programmable I/O architecture 有权
标题翻译： SERDES具有可编程I / O架构
公开(公告)号：US07208975B1
公开(公告)日：2007-04-24
申请号：US11040772
申请日：2005-01-20
申请人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
发明人： Om P. Agrawal , Jock Tomlinson , Kuang Chi , Ji Zhao , Ju Shen , Jinghui Zhu
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.
摘要翻译：在一个实施例中，可编程互连包括专用于传送高速数据的SERDES电路和专用于传送低速数据的输入/输出（I / O）电路。布线结构可配置为将SERDES电路耦合到另一个SERDES电路，到I / O电路的SERDES电路，到SERDES电路的I / O电路以及通过路由路径到另一个I / O电路的I / O电路具有确定性的路由延迟。在另一个实施例中，路由结构包括用于向SERDES电路传送高速数据和从SERDES电路传送高速数据的高速路由结构以及用于向I / O电路传送低速数据的低速路由结构。

3. 发明授权

US08022760B2 3-way Doherty amplifier with minimum output network 有权
标题翻译： 3路Doherty放大器，最小输出网络
公开(公告)号：US08022760B2
公开(公告)日：2011-09-20
申请号：US12809757
申请日：2008-12-18
申请人： Radjindrepersad Gajadharsing , Weng Chuen Edmund Neo , Marco Johannes Pelk , Leonardus Cornelis Nicolaas De Vreede , Ji Zhao
发明人： Radjindrepersad Gajadharsing , Weng Chuen Edmund Neo , Marco Johannes Pelk , Leonardus Cornelis Nicolaas De Vreede , Ji Zhao
IPC分类号： H03F3/68
CPC分类号： H03F1/08 , H03F1/0288 , H03F2200/391 , H03F2200/451 , H03F2200/543
摘要： A 3-way Doherty amplifier has an amplifier input and an amplifier output. The amplifier has a main stage, a first peak stage and a second peak stage. The amplifier has an input network connecting the amplifier input to the inputs of the stages, and an output network connecting the stages to the amplifier output. The output network implements a phase shift of 90° between the output of the main stage and the amplifier output; a phase shift of 180° between the output of the first peak stage and the amplifier output; and a phase shift of 90° between the third output and the amplifier output.
摘要翻译： 3路Doherty放大器具有放大器输入和放大器输出。该放大器具有主阶段，第一峰值阶段和第二峰值阶段。放大器具有将放大器输入连接到级的输入的输入网络，以及将级连接到放大器输出的输出网络。输出网络在主级输出与放大器输出之间实现90°的相移; 在第一峰值级的输出和放大器输出之间的相移为180°; 第三输出和放大器输出之间的相移为90°。

4. 发明授权

US06832231B1 Multiple width random number generation 失效
标题翻译：多宽度随机数生成
公开(公告)号：US06832231B1
公开(公告)日：2004-12-14
申请号：US09966967
申请日：2001-09-28
申请人： Xueping Jiang , Ming Qu , Ji Zhao
发明人： Xueping Jiang , Ming Qu , Ji Zhao
IPC分类号： G06F758
CPC分类号： G06F7/584 , G06F2207/582
摘要： Method and system for generating a multiple width (e.g., 16-bit width) pseudo-random number (PRN). Each of first and second 8-bit width PRNs is generated, using first and second LFSR configurations that incorporate first and second characteristic polynomials, at least one of which is irreducible. The first and second 8-bit PRNs are generated on a rising edge and on a falling edge, respectively, of a clock signal. The first and second 8-bit PRNs are combined by concatenation or by interleaving to form a 16-bit, or other multiple width, PRN.
摘要翻译：用于产生多个宽度（例如，16位宽度）伪随机数（PRN）的方法和系统。使用包含第一和第二特征多项式的第一和第二LFSR配置来生成第一和第二8位宽度PRN中的每一个，其中至少一个是不可约的。第一和第二8位PRN分别在时钟信号的上升沿和下降沿产生。第一和第二8位PRN通过级联或交织来组合以形成16位或其他多宽度的PRN。

5. 发明授权

US06614291B1 Low voltage, high speed CMOS CML latch and MUX devices 有权
标题翻译：低电压，高速CMOS CML锁存器和MUX器件
公开(公告)号：US06614291B1
公开(公告)日：2003-09-02
申请号：US09881950
申请日：2001-06-15
申请人： Ji Zhao , Kochung Lee , Edwin Chan
发明人： Ji Zhao , Kochung Lee , Edwin Chan
IPC分类号： H03K1762
CPC分类号： H03K3/356043 , H03K3/012 , H03K17/04106 , H03K17/693 , H03K2217/0036
摘要： A signal multiplexer system and a signal latch system for low voltage (Vdd≈1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.
摘要翻译：用于低电压（Vdd≈1.2伏）和状态之间的高速转换的信号复用器系统和信号锁存系统。插入在时钟信号电路和信号输入/输出电路之间的直流信号隔离电路允许使用双晶体管层垂直结构，为高速晶体管提供足够的净空电压（约0.3-0.4伏或更大）响应。

6. 发明申请

US20110292347A1 3D Interaction for Mobile Device 有权
标题翻译：移动设备的3D交互
公开(公告)号：US20110292347A1
公开(公告)日：2011-12-01
申请号：US12790315
申请日：2010-05-28
申请人： Chunhui Zhang , Ji Zhao , Chunshui Zhao , Rui Gao
发明人： Chunhui Zhang , Ji Zhao , Chunshui Zhao , Rui Gao
IPC分类号： G03B21/26 , G03B21/00
CPC分类号： G03B17/54 , G03B21/00 , G03B21/26
摘要： Techniques for utilizing an infrared illuminator, an infrared camera, and a projector to create a virtual 3D model of a real 3D object in real time for users' interaction with the real 3D object.
摘要翻译：用于利用红外照明器，红外摄像机和投影仪实时地创建真实3D对象的虚拟3D模型的技术，用于与真实3D对象的交互。

7. 发明申请

US20100310576A1 COMPOSITIONS AND METHODS COMPRISING ASPARTYL-tRNA SYNTHETASES HAVING NON-CANONICAL BIOLOGICAL ACTIVITIES 审中-公开
标题翻译：包含具有非经济生物活性的ASPARTYL-tRNA合成酶的组合物和方法
公开(公告)号：US20100310576A1
公开(公告)日：2010-12-09
申请号：US12751358
申请日：2010-03-31
申请人： Ryan A. Adams , Fei Hong , Ji Zhao , Kristi Piehl , Eva R. Armour , Kenny D'Arigo , Leslie A. Greene , Eve Merriman
发明人： Ryan A. Adams , Fei Hong , Ji Zhao , Kristi Piehl , Eva R. Armour , Kenny D'Arigo , Leslie A. Greene , Eve Merriman
IPC分类号： A61K39/395 , C12N9/00 , C07H21/00 , C12N15/63 , C12N5/10 , C07K16/18 , C07K2/00 , G01N33/573 , G01N33/566 , A61K38/43 , A61K31/7088 , A61K38/02 , A61P35/00 , A61P25/00 , A61P9/00 , A61P31/00 , A61P37/02 , A61P29/00 , A61P3/00 , C12N5/07
CPC分类号： C12N9/93 , A61K38/00 , C07K16/00 , C07K2319/30 , C07K2319/33 , C12Q1/25 , C12Y601/01012 , G01N33/573 , G01N2500/00 , Y02A50/385 , Y02A50/389 , Y02A50/411 , Y02A50/423 , Y02A50/463 , Y02A50/53 , Y02A50/58
摘要： Isolated aspartyl-tRNA synthetase polypeptides and polynucleotides having non-canonical biological activities are provided, as well as compositions and methods related thereto.
摘要翻译：提供了分离的天冬氨酰-tRNA合成酶多肽和具有非规范生物活性的多核苷酸，以及与其相关的组合物和方法。

8. 发明授权

US06429692B1 High speed data sampling with reduced metastability 有权
标题翻译：具有降低亚稳态的高速数据采样
公开(公告)号：US06429692B1
公开(公告)日：2002-08-06
申请号：US09885243
申请日：2001-06-19
申请人： Edwin Chan , Kochung Lee , Ji Zhao
发明人： Edwin Chan , Kochung Lee , Ji Zhao
IPC分类号： H03K19094
CPC分类号： H03K3/356043 , H03K3/0375
摘要： A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.
摘要翻译：一种包括数据跟踪电路和数据锁存电路的数据采样系统，其通过两个电路的竞争降低产生亚稳态的可能性，其中在转换时间间隔内进行数据采样。提供组合的锁存和弱化跟踪电路，其中跟踪操作在锁存器解除有效逻辑状态之后不能改变来自锁存操作的输出信号。

9. 发明授权

US5861647A VLSI capacitors and high Q VLSI inductors using metal-filled via plugs 失效
标题翻译： VLSI电容器和使用金属填充通孔插头的高Q VLSI电感器
公开(公告)号：US5861647A
公开(公告)日：1999-01-19
申请号：US726311
申请日：1996-10-02
申请人： Ji Zhao , Chih Sieh Teng
发明人： Ji Zhao , Chih Sieh Teng
IPC分类号： H01L21/02 , H01L23/522 , H01L29/00 , H01L27/02
CPC分类号： H01L28/10 , H01L23/5223 , H01L23/5227 , H01L28/40 , H01L2924/0002
摘要： Disclosed are methods of making inductors and capacitors, comprising filling a via in a dielectric disposed between two metal layers with a metal plug. The plug comprises tungsten, aluminum or copper and extends the length of the metal layers. The plug connects the two metal layers to form the inductor. Two plugs can be formed so as to connect the two metal layers so as to form a parallel plate capacitor.
摘要翻译：公开了制造电感器和电容器的方法，包括在设置在两个金属层之间的电介质中用金属插塞填充通孔。插头包括钨，铝或铜并延伸金属层的长度。插头连接两个金属层以形成电感器。可以形成两个插头以便连接两个金属层以形成平行板电容器。

10. 发明授权

US06825733B1 Low jitter integrated phase locked loop with broad tuning range 有权
标题翻译：具有宽调谐范围的低抖动集成锁相环
公开(公告)号：US06825733B1
公开(公告)日：2004-11-30
申请号：US10300190
申请日：2002-11-20
申请人： Ming Qu , Ji Zhao
发明人： Ming Qu , Ji Zhao
IPC分类号： H03B2100
CPC分类号： H03L7/18 , H03L7/095 , H03L7/0995 , H03L7/107 , Y10S331/02
摘要： System and method for providing a low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.
摘要翻译：用于提供具有宽调谐范围（1GHz至10GHz或更大）的低噪声信号的系统和方法，相关抖动不超过目标输出信号的选定周期的约10％。在第一级中，基于环的VCO锁相环系统提供具有一些相关噪声的宽调谐范围，并且第一状态中的第二级相对是透明的，基于频率没有实质的差分衰减。在实现相位锁定之后，基于输入信号频率，第二级被切换到具有低相关噪声和高差分衰减的第二状态。

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