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1. 发明授权

US5524254A Scheme for interlocking line card to an address recognition engine to support plurality of routing and bridging protocols by using network information look-up database 失效
标题翻译：将互联线卡与地址识别引擎相结合的方案，通过使用网络信息查找数据库来支持多个路由和桥接协议
公开(公告)号：US5524254A
公开(公告)日：1996-06-04
申请号：US269997
申请日：1994-07-01
申请人： Fearghal Morgan , Joseph O'Callaghan , Michael J. Seaman , John Rigby , Andrew Walton , Una M. Quinlan , Stewart F. Bryant
发明人： Fearghal Morgan , Joseph O'Callaghan , Michael J. Seaman , John Rigby , Andrew Walton , Una M. Quinlan , Stewart F. Bryant
IPC分类号： G06F13/00 , H04L12/46 , H04L29/06 , H04L29/12
CPC分类号： H04L29/12801 , H04L12/46 , H04L29/12009 , H04L29/12839 , H04L45/742 , H04L61/6004 , H04L61/6022 , H04L69/18 , H04L69/22
摘要： The present invention provides an interlock scheme for use between a line card and an address recognition apparatus. The interlock scheme reduces the total number of read/write operations over a backplane bus coupling the line card to the address recognition apparatus required to complete a request/response transfer. Thus, the line card and address recognition apparatus are able to perform a large amount of request/response transfers with a high level of system efficiency. Generally, the interlocking scheme according to the present invention merges each ownership information storage location into the location of the request/response memory utilized to store the corresponding request/response pair to reduce data transfer traffic over the backplane bus. According to another feature of the interlock scheme of the present invention, each of the line card and the address recognition engine includes a table for storing information relating to a plurality of database specifiers. Each of the database specifiers contains control information for the traversal of a lookup database used by the address recognition apparatus. At the time the processor of a line card generates a request for the address recognition apparatus, it will analyze the protocol type information contained in the header of a data packet. The processor will utilize the protocol type information as a look-up index to its table of database specifiers for selection of one of the database specifiers. The processor will then insert an identification of the selected database specifier into the request with the network address extracted from the data packet.
摘要翻译：本发明提供了一种用于线卡和地址识别装置之间的互锁方案。互锁方案减少了通过将线卡耦合到完成请求/响应传输所需的地址识别装置的背板总线上的读/写操作的总数。因此，线卡和地址识别装置能够以高水平的系统效率执行大量的请求/响应传送。通常，根据本发明的联锁方案将每个所有权信息存储位置合并到用于存储相应的请求/响应对的请求/响应存储器的位置，以减少背板总线上的数据传输流量。根据本发明的联锁方案的另一特征，线卡和地址识别引擎中的每一个都包括用于存储与多个数据库说明符有关的信息的表。每个数据库说明符包含用于遍历由地址识别装置使用的查找数据库的控制信息。当线卡的处理器产生对地址识别装置的请求时，它将分析包含在数据分组头部中的协议类型信息。处理器将利用协议类型信息作为其数据库说明符表的查找索引，以选择其中一个数据库说明符。然后处理器将所选择的数据库说明符的标识插入到从数据包中提取的网络地址的请求中。

2. 发明授权

US5519858A Address recognition engine with look-up database for storing network information 失效
标题翻译：地址识别引擎，具有用于存储网络信息的查找数据库
公开(公告)号：US5519858A
公开(公告)日：1996-05-21
申请号：US819490
申请日：1992-01-10
申请人： Andrew Walton , Una M. Quinlan , Stewart F. Bryant , Michael J. Seaman , John Rigby , Fearghal Morgan , Joseph O'Callaghan
发明人： Andrew Walton , Una M. Quinlan , Stewart F. Bryant , Michael J. Seaman , John Rigby , Fearghal Morgan , Joseph O'Callaghan
IPC分类号： G06F17/30 , H04L12/56 , H04L29/06
CPC分类号： H04L29/06
摘要： The present invention is directed to an address recognition apparatus including an address recognition engine coupled to a look-up database. The look-up database is arranged to store network information relating to network addresses. The look-up database includes a primary database and a secondary database. The address recognition engine accepts as an input a network address for which network information is required. The address recognition engine uses the network address as an index to the primary database. The primary database comprises a multiway tree node structure (TRIE) arranged for traversal of the nodes as a function of preselected segments of the network address and in a fixed sequence of the segments to locate a pointer to an entry in the secondary database. The entry in the secondary database pointed to by the primary database pointer contains the network information corresponding to the network address. The address recognition engine includes a table for storing a plurality of database specifiers. Each of the database specifiers contains control information for the traversal of the primary and secondary databases. In addition, each of the nodes in the primary database and each of the entries in the secondary database is provided with control data structures that are programmable to control the traversal of the database.
摘要翻译：本发明涉及包括耦合到查找数据库的地址识别引擎的地址识别装置。查找数据库被设置为存储与网络地址有关的网络信息。查找数据库包括主数据库和辅助数据库。地址识别引擎接受需要网络信息的网络地址作为输入。地址识别引擎使用网络地址作为主数据库的索引。主数据库包括多路树节点结构（TRIE），其被布置为根据网络地址的预选段的顺序遍历节点，并且在段的固定序列中定位到辅助数据库中的条目的指针。主数据库指针指向的辅助数据库中的条目包含与网络地址对应的网络信息。地址识别引擎包括用于存储多个数据库说明符的表。每个数据库说明符都包含用于遍历主数据库和辅助数据库的控制信息。此外，主数据库中的每个节点和辅助数据库中的每个条目都具有可编程以控制数据库遍历的控制数据结构。

3. 发明授权

US5202884A Multiplexing scheme for modem control signals 失效
标题翻译：调制解调器控制信号的多路复用方案
公开(公告)号：US5202884A
公开(公告)日：1993-04-13
申请号：US722686
申请日：1991-06-28
申请人： Ciaran B. Close , Bryan T. Campbell , Una M. Quinlan
发明人： Ciaran B. Close , Bryan T. Campbell , Una M. Quinlan
IPC分类号： H04L29/10 , G06F13/38
CPC分类号： G06F13/385
摘要： In an apparatus to couple a plurality of line interfaces with corresponding modems ports, status and control signals are time-division-multiplexed (TDM) into a data stream before being exchanged between the devices. This substantially reduces the number of communication wires required and allows for several modems to be coupled in close proximity to a line interface card. Packet recognition circuitry coupled to the modem ports insures that signals in the TDM data stream are transmitted to the appropriate modem ports.

4. 发明授权

US6078949A Scheme for interlocking and transferring information between devices in a computer system 失效
标题翻译：用于在计算机系统中的设备之间联锁和传送信息的方案
公开(公告)号：US6078949A
公开(公告)日：2000-06-20
申请号：US294765
申请日：1994-08-23
申请人： Una M. Quinlan
发明人： Una M. Quinlan
IPC分类号： G06F9/46 , G06F9/52 , G06F13/16 , G06F15/16 , G06F15/177 , G06F15/167
CPC分类号： G06F13/1652
摘要： A scheme for interlocking two devices in a computer system for the performance of request/response transfers between the two devices. The scheme provides a request/response memory including a plurality of entries, each of the entries having a request storage memory space for storing a request and a response storage memory space for storing a corresponding response. Each request storage memory space and response storage memory space includes a preselected area for the storage of ownership information relating to the request/response pair stored in the respective entry so that ownership information can be read and written in the same read/write operations utilized in respect of the corresponding request/response pair.
摘要翻译：用于在计算机系统中互锁两个设备以在两个设备之间执行请求/响应传输的方案。该方案提供包括多个条目的请求/响应存储器，每个条目具有用于存储请求的请求存储空间和用于存储相应响应的响应存储存储空间。每个请求存储空间和响应存储存储器空间包括用于存储与存储在相应条目中的请求/响应对相关的所有权信息的预选区域，使得所有权信息可以被读取和写入相同的读/写操作中尊重相应的请求/响应对。

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