专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5825203A Variable logic integrated circuit device having connections through switch matrix and top layers for inter-cell connections 失效
标题翻译：可变逻辑集成电路器件具有通过开关矩阵和顶层连接的单元间连接的连接
公开(公告)号：US5825203A
公开(公告)日：1998-10-20
申请号：US747339
申请日：1996-11-12
申请人： Mitsugu Kusunoki , Nobuo Tamba
发明人： Mitsugu Kusunoki , Nobuo Tamba
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17792
摘要： A variable logic integrated circuit device formed on a semiconductor chip comprising variable logic blocks and switch matrices laid out alternately in the X and Y directions in a checkerboard pattern. Above the variable logic blocks is a block interconnection wiring arrangement formed by multiple-layer wiring techniques. The variable logic blocks and switch matrices are wired into circuits respectively by a lower wiring layer in the multiple wiring layer setup of the chip. The block interconnection wiring is formed by an upper wiring layer extending above the variable logic blocks and included in the multiple wiring layer setup. The switch matrices are used to connect the block interconnection lines to one another as well as to the variable logic blocks.
摘要翻译：形成在半导体芯片上的可变逻辑集成电路器件，其包括以棋盘图案在X和Y方向交替布置的可变逻辑块和开关矩阵。可变逻辑块之上是通过多层布线技术形成的块互连布线布置。可变逻辑块和开关矩阵分别通过芯片的多个布线层设置中的下布线层布线到电路中。块互连布线由在可变逻辑块之上延伸并包括在多个布线层设置中的上布线层形成。开关矩阵用于将块互连线彼此连接到可变逻辑块。

2. 发明授权

US5852365A Variable logic circuit and semiconductor integrated circuit using the same 失效
标题翻译：可变逻辑电路和半导体集成电路使用相同
公开(公告)号：US5852365A
公开(公告)日：1998-12-22
申请号：US712554
申请日：1996-09-13
申请人： Nobuo Tamba , Mitsugu Kusunoki , Takeshi Miyazaki , Akira Masaki , Akira Yamagiwa
发明人： Nobuo Tamba , Mitsugu Kusunoki , Takeshi Miyazaki , Akira Masaki , Akira Yamagiwa
IPC分类号： H03K19/177 , H03K19/173 , H03K19/082 , H03K7/38
CPC分类号： H03K19/1737
摘要： A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned transistor and is turned on or off by an input signal, a transistor which produces a voltage depending on the conduction states of the above-mentioned transistors, and transfer means which conducts or does not conduct the produced voltage to the output terminal depending on a select signal.
摘要翻译：可变逻辑电路包括存储单元，根据存储在存储单元中的数据导通或截止的晶体管，与上述晶体管串联连接并通过输入信号导通或截止的晶体管，晶体管，其根据上述晶体管的导通状态产生电压，以及根据选择信号将导通或不导通所产生的电压的输出装置输出到输出端。

3. 发明授权

US5512497A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US5512497A
公开(公告)日：1996-04-30
申请号：US272312
申请日：1994-07-08
申请人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
发明人： Takahide Ikeda , Kouichirou Yamada , Osamu Saito , Masanori Odaka , Nobuo Tamba , Katsumi Ogiue , Atsushi Hiraishi , Atsuo Watanabe , Mitsuru Hirao , Akira Fukami , Masayuki Ohayashi , Tadashi Kuramoto
IPC分类号： H01L21/28 , H01L21/285 , H01L21/8249 , H01L27/06 , H01L21/265 , H01L21/8238
CPC分类号： H01L21/28026 , H01L21/28525 , H01L21/8249 , H01L27/0623 , Y10S148/009
摘要： Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
摘要翻译：公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

4. 发明授权

US4903093A Semiconductor integrated circuit device double isolated CMOS input protection resistor 失效
标题翻译：半导体集成电路器件双隔离CMOS输入保护电阻
公开(公告)号：US4903093A
公开(公告)日：1990-02-20
申请号：US199671
申请日：1988-05-27
申请人： Akira Ide , Koichi Motohashi , Masanori Odaka , Nobuo Tamba
发明人： Akira Ide , Koichi Motohashi , Masanori Odaka , Nobuo Tamba
IPC分类号： H01L21/8249 , H01L21/331 , H01L27/02 , H01L27/06 , H01L27/10 , H01L27/105 , H01L29/73 , H01L29/732
CPC分类号： H01L27/0288 , H01L27/0251 , H01L27/105
摘要： In a semiconductor integrated circuit device, input protective elements have current limiting resistors which are diffused resistors of a second conductivity type formed in a first semiconductor region of a first conductivity type isolated electrically by a second semiconductor region of the second conductivity type, with the first conductivity type semiconductor region being in a floating state electrically. The input protective elements create less leak current and have high electrostatic durability.
摘要翻译：在半导体集成电路器件中，输入保护元件具有限流电阻，其是第二导电类型的扩散电阻器，形成在由第二导电类型的第二半导体区域电隔离的第一导电类型的第一半导体区域中，导电型半导体区域处于浮置状态。输入保护元件产生更少的漏电流并具有高静电耐久性。

5. 发明授权

US5457412A Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
标题翻译：半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作
公开(公告)号：US5457412A
公开(公告)日：1995-10-10
申请号：US149935
申请日：1993-11-10
申请人： Nobuo Tamba , Masanori Odaka , Toshiro Hiramoto , Masayuki Ohayashi , Kayoko Saito
发明人： Nobuo Tamba , Masanori Odaka , Toshiro Hiramoto , Masayuki Ohayashi , Kayoko Saito
IPC分类号： G11C11/413 , H01L21/8249 , H01L27/06 , H03K19/0175 , H03K19/08
CPC分类号： H03K19/017527
摘要： A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.
摘要翻译：提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和电路。该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

6. 发明授权

US5255225A Semiconductor integrated circuit device and memory consisting of semiconductor integrated circuit 失效
标题翻译：半导体集成电路器件和存储器由半导体集成电路组成
公开(公告)号：US5255225A
公开(公告)日：1993-10-19
申请号：US845557
申请日：1992-03-04
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Hisayuki Higuchi , Youji Idei , Kenichi Ohata , Yoshiaki Sakurai , Masanori Odaka , Goro Kitsukawa , Nobuo Tamba , Masayuki Ohayashi , Toshiro Hiramoto , Kayoko Saito
IPC分类号： G11C5/14 , G11C7/10 , G11C11/40
CPC分类号： G11C7/1057 , G11C5/147 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided.A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor.The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.
摘要翻译：提供一种包括电平转换电路的半导体集成电路器件，其中电路的简化和操作速度的提高已经达到。通过包括接收输入信号和参考电压的差分晶体管的电流开关电路将被放大到所需信号电平的一对互补输出信号输入到一对发射极跟随器电路中。射极跟随器输出晶体管由来自一个射极跟随器电路的输出信号驱动，而在输出晶体管和用作负载的电流源之间提供的N沟道MOSFET由另一个射极跟随器电路的输出信号驱动到从输出晶体管的发射极获得电平放大的输出信号。电路装置的运行速度可以通过电流开关电路确保互补输出信号的达到输出幅度所需的电平的简单电路而增加到高电平，放大的互补信号被输入射极跟随器电路以直接驱动输出晶体管。

7. 再颁专利

USRE38545E1 Semiconductor memory device 有权
公开(公告)号：USRE38545E1
公开(公告)日：2004-07-06
申请号：US09636642
申请日：2000-08-08
申请人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
发明人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
IPC分类号： H01L2976
CPC分类号： G11C11/412 , H01L27/1104
摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction. More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.

8. 发明授权

US5360988A Semiconductor integrated circuit device and methods for production thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5360988A
公开(公告)日：1994-11-01
申请号：US903202
申请日：1992-06-23
申请人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
发明人： Takayuki Uda , Toshiro Hiramoto , Nobuo Tamba , Hisashi Ishida , Kazuhiro Akimoto , Masanori Odaka , Tasuku Tanaka , Jun Hirokawa , Masayuki Ohayashi
IPC分类号： H01L21/60 , H01L23/055 , H01L23/525 , H01L27/118 , H01L23/48 , F42C19/12 , G06F15/60 , H01L21/285
CPC分类号： H01L24/81 , H01L23/055 , H01L23/5256 , H01L24/11 , H01L27/118 , H01L2224/0401 , H01L2224/05567 , H01L2224/05572 , H01L2224/1147 , H01L2224/1148 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/73253 , H01L2224/81801 , H01L23/3171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/0107 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/19043 , H01L2924/3011 , H01L2924/3025
摘要： Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.
摘要翻译：公开了半导体集成电路装置及其制造方法。本发明的实施例是一种半导体芯片，其包括构成其中形成的冗余电路的一部分的熔丝，该熔丝由与CCB凸块基板金属相同的部件制成。在CCB凸块基板金属的图案化期间，熔丝同时被图案化。这涉及使用芯片中的电极导体图案的成分的至少一部分来形成保险丝。保险丝的切割区域仅由构成基板的金属层中的一个构成。半导体芯片的主平面具有至少形成在保险丝的切割区域上的保险丝保护膜，用于保护保险丝。在操作中，使用冗余信号的开关控制下的开关MOSFET来选择两个传输路径中的一个，一个传送地址信号或解码信号，另一个传送参考电压。这样可以将故障电路替换为相应的冗余电路。

9. 发明授权

US4984058A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4984058A
公开(公告)日：1991-01-08
申请号：US225357
申请日：1988-07-28
申请人： Shuuichi Miyaoka , Nobuo Tamba , Toshikazu Arai , Hiroshi Higuchi , Hisayuki Higuchi
发明人： Shuuichi Miyaoka , Nobuo Tamba , Toshikazu Arai , Hiroshi Higuchi , Hisayuki Higuchi
IPC分类号： H01L27/11 , G11C11/401 , H01L21/3205 , H01L21/8244 , H01L23/52 , H01L23/528 , H01L27/02
CPC分类号： H01L27/0214 , H01L23/5286 , H01L24/06 , H01L2924/10253 , H01L2924/14 , H01L2924/3011 , Y10S257/915
摘要： In a semiconductor integrated circuit device having memory cell arrays, power source wirings are provided on the memory cell array in parallel with the long side of the memory cell array, thereby strengthening the power source wirings without increasing a chip size and planning reduction in power source impedances.
摘要翻译：在具有存储单元阵列的半导体集成电路器件中，与存储单元阵列的长边平行地在存储单元阵列上提供电源布线，从而在不增加芯片尺寸和规划电源减少的情况下加强电源布线阻力。

10. 发明授权

US5854497A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5854497A
公开(公告)日：1998-12-29
申请号：US773312
申请日：1996-12-24
申请人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
发明人： Toshiro Hiramoto , Nobuo Tamba , Motoki Kasai
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , H01L29/76 , G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.
摘要翻译：一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式