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1. 发明授权

US06864711B2 Programmable array logic circuit whose product and input line junctions employ single bit non-volatile ferromagnetic cells 失效
标题翻译：其可编程阵列逻辑电路，其产品和输入线路结采用单位非易失性铁磁电池
公开(公告)号：US06864711B2
公开(公告)日：2005-03-08
申请号：US10239133
申请日：2001-01-20
申请人： Richard M. Lienau
发明人： Richard M. Lienau
IPC分类号： G11C7/22 , G11C11/15 , H03K17/687 , H03K19/177 , H03K7/38
CPC分类号： H03K17/6871 , G11C7/22 , G11C11/15 , G11C2207/2227 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array.
摘要翻译：一种可编程阵列逻辑电路，其临时存储器电路采用单位非易失性铁磁存储器单元。铁磁存储器单元或位存储数据，即使没有电力提供给电路，从而在可编程逻辑电路的操作期间节省功率，并且确保在暂时停电时不会丢失数据。此外，铁磁单元提供对数据的不确定数量的切换动作，而不降低存储数据的能力。本发明提供一种集成电路，包括其中具有产品线和输入线的可编程逻辑电路阵列和存储寄存器电路。存储寄存器电路具有铁磁位和传感器，其耦合以存储剩余控制信号和输出晶体管，耦合以响应于其栅极上的剩余控制信号，并耦合在输入和产品线之间。此外，集成电路还可以包括逻辑AND阵列和逻辑OR阵列。

2. 发明授权

US6020758A Partially reconfigurable programmable logic device 失效
标题翻译：部分可重新配置的可编程逻辑器件
公开(公告)号：US6020758A
公开(公告)日：2000-02-01
申请号：US615341
申请日：1996-03-11
申请人： Rakesh H. Patel , Kevin A. Norman
发明人： Rakesh H. Patel , Kevin A. Norman
IPC分类号： H03K19/177 , H03K19/173 , H03K7/38
CPC分类号： H03K19/17752 , H03K19/17756
摘要： Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.
摘要翻译：公开了能够动态部分重新配置的可编程逻辑器件（PLD）的各种实施例。 PLD提供用于全部或部分更改其配置数据的电路，而不会停止操作，也不会丢失PLD的任何逻辑状态。在一个实施例中，将数据注入电路添加到FIFO架构以允许用户在随机位置注入数据而不会干扰PLD的功能。在另一个实施例中，PLD架构被设计为提供配置位的地址宽或帧宽访问。这允许地址宽配置和重新配置。

3. 发明授权

US5907248A FPGA interconnect structure with high-speed high fanout capability 失效
标题翻译： FPGA互连结构具有高速高扇出功能
公开(公告)号：US5907248A
公开(公告)日：1999-05-25
申请号：US20369
申请日：1998-02-09
申请人： Trevor J. Bauer , Steven P. Young
发明人： Trevor J. Bauer , Steven P. Young
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17796 , H03K19/1737 , H03K19/17704
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away. According to a second aspect of the invention, high fanout signals can be distributed to any tile in the array. A signal on a horizontal long line traverses a row of tiles, in which it makes contact with the logic block in each tile through hex lines and single-length lines. The horizontal single-length lines connected to some horizontal hex lines can programmably drive vertical long lines. Using these programmable connections, the signal on the horizontal long line bus is transferred to the vertical long lines. From the vertical long lines, a high-fanout signal is delivered to an array of tiles.
摘要翻译：本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径和瓷砖有一段距离。可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片之外，然后继续并连接到瓦片六瓦片。在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。根据本发明的第二方面，高扇出信号可以分布到阵列中的任何瓦片。水平长线上的信号穿过一排瓦片，通过十六进制线和单条线与其接触每个瓦片中的逻辑块。连接到一些水平六边形线的水平单线可以编程地驱动垂直的长线。使用这些可编程连接，水平长线总线上的信号传输到垂直长线。从垂直长线，高扇出信号被传送到一组瓦片。

4. 发明授权

US5883525A FPGA architecture with repeatable titles including routing matrices and logic matrices 失效
标题翻译：具有可重复标题的FPGA架构，包括路由矩阵和逻辑矩阵
公开(公告)号：US5883525A
公开(公告)日：1999-03-16
申请号：US943890
申请日：1997-10-03
申请人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
发明人： Danesh Tavana , Wilson K. Yee , Victor A. Holen
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
摘要翻译： FPGA架构提供了通过路由矩阵直接连接到相邻逻辑元件和间接连接的逻辑元件。逻辑元件和路由矩阵的一部分被形成为瓦片的一部分，并且瓦片被连接以形成可选择尺寸的阵列。路由矩阵包括仅从一个瓦片连接到下一个瓦片的路由线路，以及通过几个瓦片或整个芯片延长更长距离的路由线路。这种组合是通过形成各个瓷砖来实现的，所有这些瓷砖都是相同的。

5. 发明授权

US5847578A Programmable multiplexing input/output port 失效
标题翻译：可编程复用输入/输出端口
公开(公告)号：US5847578A
公开(公告)日：1998-12-08
申请号：US780527
申请日：1997-01-08
申请人： Michael Donald Noakes , Charles W. Selvidge , Anant Argarwal , Jonathan Babb , Matthew L. Dahl
发明人： Michael Donald Noakes , Charles W. Selvidge , Anant Argarwal , Jonathan Babb , Matthew L. Dahl
IPC分类号： H03K19/173 , H03K7/38 , H03K19/00
CPC分类号： G06F17/5054 , H03K19/1732 , H03K19/1737
摘要： A programmable logic circuit includes a programmable logic array which generates a plurality of output signals for output from a single port on the programmable logic circuit, and which processes a plurality of input signals received from a single port on the programmable logic circuit. The programmable logic circuit also includes multiplexing means for receiving the plurality of output signals generated by the programmable logic array and for multiplexing the plurality of output signals. An output port outputs, from the programmable logic circuit, the multiplexed plurality of output signals generated by the programmable logic array. An input port receives a multiplexed plurality of input signals, and a demultiplexing means demultiplexes the multiplexed plurality of input signals and configurably communicates the demultiplexed plurality of input signals to the programmable logic array. This demultiplexing means and the multiplexing means are each operable at a clock speed which is different from a clock speed of the programmable logic array.
摘要翻译：可编程逻辑电路包括可编程逻辑阵列，其产生用于从可编程逻辑电路上的单个端口输出的多个输出信号，并且其处理从可编程逻辑电路上的单个端口接收的多个输入信号。可编程逻辑电路还包括用于接收由可编程逻辑阵列产生的多个输出信号并用于复用多个输出信号的多路复用装置。输出端口从可编程逻辑电路输出由可编程逻辑阵列产生的复用的多个输出信号。输入端口接收复用的多个输入信号，并且解复用装置对多路复用的多个输入信号进行解复用，并将可解复用的多个输入信号可配置地传送到可编程逻辑阵列。该解复用装置和多路复用装置各自以与可编程逻辑阵列的时钟速度不同的时钟速度工作。

6. 发明授权

US5684412A Cell forming part of a customizable logic array 失效
标题翻译：单元格形成可定制逻辑阵列的一部分
公开(公告)号：US5684412A
公开(公告)日：1997-11-04
申请号：US516990
申请日：1995-08-18
申请人： Uzi Yoeli , Eran Rotem , Yehuda Yizraeli
发明人： Uzi Yoeli , Eran Rotem , Yehuda Yizraeli
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118 , H03K19/173 , H03K7/38 , H03K19/0175
CPC分类号： H03K19/1737
摘要： A cell forming part of a customizable logic array and including at least first and second different multiplexers, an output of the first multiplexer being connected to an input of the second multiplexer.
摘要翻译：形成可定制逻辑阵列的一部分并且包括至少第一和第二不同复用器的单元，第一多路复用器的输出连接到第二多路复用器的输入。

7. 发明授权

US07068071B1 Integrated circuit with overclocked dedicated logic circuitry 有权
标题翻译：具有超频专用逻辑电路的集成电路
公开(公告)号：US07068071B1
公开(公告)日：2006-06-27
申请号：US10970962
申请日：2004-10-22
申请人： Roger B. Milne , Jonathan B. Ballagh
发明人： Roger B. Milne , Jonathan B. Ballagh
IPC分类号： H03K7/38
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/1774
摘要： An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal having a first frequency. A dedicated logic circuit embedded within the programmable logic device is operable using a second clock signal synchronized with the first clock signal and having a second frequency, the second frequency being a multiple of the first frequency. An interface coupled between one or more of the programmable logic blocks and the dedicated logic circuit includes multiplexer circuitry to multiplex output signals produced by the one or more programmable logic blocks among input terminals of the dedicated logic circuit.
摘要翻译：描述了具有超频嵌入式逻辑电路的集成电路。在一个示例中，可编程逻辑器件包括可使用具有第一频率的第一时钟信号操作的可编程逻辑块。嵌入在可编程逻辑器件内的专用逻辑电路使用与第一时钟信号同步并具有第二频率的第二时钟信号来工作，第二频率是第一频率的倍数。耦合在一个或多个可编程逻辑块和专用逻辑电路之间的接口包括多路复用器电路，用于在专用逻辑电路的输入端之间复用由一个或多个可编程逻辑块产生的输出信号。

8. 发明授权

US5880598A Tile-based modular routing resources for high density programmable logic device 失效
标题翻译：基于瓦片的模块化路由资源，用于高密度可编程逻辑器件
公开(公告)号：US5880598A
公开(公告)日：1999-03-09
申请号：US781251
申请日：1997-01-10
申请人： Khue Duong
发明人： Khue Duong
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17796
摘要： Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs. A corner tile is also provided that permits interconnection between horizontal and vertical tiles. The tiles are modular in nature so the number of tiles provided within an array and their placement are determined based on the array's particular need for routing resources, e.g., an array can have one, two or more tiles associated with a row or column of CLBs in areas of the chip where congestion is typically encountered. Each tile of the present invention can also include a plurality of switch matrices, buffers, or other active gates to facilitate signal routing.
摘要翻译：可以被操纵为电路“单元”的信号路由资源块，因为它们可以容易地在可编程逻辑器件（例如现场可编程门阵列（FPGA））上表征和实现。在一个实施例中，提供垂直布置和水平布置布线资源瓦片。路由资源瓦片可以被选择性地添加到被确定为容易发生高信号拥塞的可编程逻辑设备的区域中，例如阵列的中心部分以及阵列周边。额外的路由资源瓦片简化了复杂逻辑功能的路由，并提高了构成阵列的可配置逻辑块（CLB）的利用率。可以在CLB阵列内水平或垂直的任何位置将瓦片定位在阵列内。具体来说，放置可以在芯片的核心中，也可以沿着周边，每个瓦片提供到CLB内的现有路由资源（例如，输入/输出端口）的可编程连接。还提供了一个角瓦，可以允许水平和垂直瓦片之间的互连。瓦片本质上是模块化的，因此阵列中提供的瓦片数量及其布局是基于阵列对路由资源的特殊需求来确定的，例如，阵列可以具有与CLB的行或列相关联的一个，两个或更多个瓦片在通常遇到拥塞的芯片的区域中。本发明的每个瓦片还可以包括多个开关矩阵，缓冲器或其他有源门以便于信号路由。

9. 发明授权

US5872463A Routing in programmable logic devices using shared distributed programmable logic connectors 失效
标题翻译：使用共享分布式可编程逻辑连接器在可编程逻辑器件中进行路由
公开(公告)号：US5872463A
公开(公告)日：1999-02-16
申请号：US710862
申请日：1996-09-23
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H03K19/177 , H03K7/38
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： The output signals of the logic regions in a programmable logic integrated circuit device are programmably connectable to output bus conductors. Each such output signal can be applied to any of several of these conductors, and each conductor can receive any of several output signals. Each output bus conductor is connectable to one or more output drivers (e.g., through a programmable connector it shares with another output bus conductor). The output drivers can drive more general interconnection resources of the device. This device architecture increases logic region output signal routing flexibility and/or allows the number of output drivers to be decreased (i.e., by making more efficient use of the output drivers that are provided).
摘要翻译：可编程逻辑集成电路器件中的逻辑区域的输出信号可编程地连接到输出总线导体。每个这样的输出信号可以被施加到这些导体中的几个中的任何一个，并且每个导体可以接收几个输出信号中的任何一个。每个输出总线导体可连接到一个或多个输出驱动器（例如，通过与另一个输出总线导体共享的可编程连接器）。输出驱动器可以驱动设备的更一般的互连资源。该器件架构增加了逻辑区域输出信号路由的灵活性和/或允许减少输出驱动器的数量（即，通过更有效地使用所提供的输出驱动器）。

10. 发明授权

US5821772A Programmable address decoder for programmable logic device 失效
标题翻译：可编程逻辑器件的可编程地址解码器
公开(公告)号：US5821772A
公开(公告)日：1998-10-13
申请号：US694650
申请日：1996-08-07
申请人： Randy T. Ong , Edel M. Young
发明人： Randy T. Ong , Edel M. Young
IPC分类号： H03K19/177 , H03K19/173 , H03K7/38
CPC分类号： H03K19/17748 , H03K19/1776
摘要： For an FPGA having a configuration memory arranged in rows and columns, a programmable address decoder with a counter selects the order in which columns of memory cells will be programmed and selects which columns of memory cells are programmed. The decoder structure addresses a particular column only when an address provided by the counter matches an address in the memory cells of the decoder for that column. Bitstreams intended for older devices can be successfully loaded into newer devices. Bitstreams developed for future devices with additional features can be loaded into devices with fewer features, and the additional features are not used. The counter can be set to count not in sequential order so that if extra columns are provided, a defective column of the FPGA controlled by a corresponding column of configuration memory cells can be bypassed.
摘要翻译：对于具有以行和列排列的配置存储器的FPGA，具有计数器的可编程地址解码器选择存储器单元的列将被编程的顺序，并选择哪一列存储器单元被编程。仅当由计数器提供的地址与该列的解码器的存储单元中的地址匹配时，解码器结构才能寻址特定的列。用于旧设备的比特流可以成功加载到较新的设备中。为具有附加功能的未来设备开发的Bitstream可以加载到具有较少功能的设备中，并且不使用其他功能。可以将计数器设置为不按顺序计数，以便如果提供额外的列，则可以绕过由相应的配置存储单元列控制的FPGA的缺陷列。

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