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1. 发明授权

US5576237A Method of manufacturing a capacitor coupled contactless imager with high resolution and wide dynamic range 失效
标题翻译：制造具有高分辨率和宽动态范围的电容耦合非接触式成像仪的方法
公开(公告)号：US5576237A
公开(公告)日：1996-11-19
申请号：US543960
申请日：1995-10-17
申请人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
发明人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
IPC分类号： H01L27/105 , H01L27/146 , H01L31/11 , H01L21/8222
CPC分类号： H01L31/1105 , H01L27/105 , Y10S148/124
摘要： A capacitor coupled contactless imager structure and a method of manufacturing the structure results in a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter content and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.
摘要翻译：电容器耦合的非接触式成像器结构和制造该结构的方法产生一种光电晶体管，其结构包括形成在P型半导体材料中的N型集电极区域。在集电区域形成P型基极区域。形成与P型基极区域的表面接触的n掺杂多晶硅发射极触点，使得在基极区域中形成n +外延区域作为光电晶体管的发射极。二氧化硅将poly1发射体含量和基底区域的暴露表面与部分覆盖基极区域的约3000-4000厚的poly2层分离; CMOS外围器件的栅极也是poly2。基极区域上的poly2用作成像器结构的基极耦合电容器和行导体。 poly2电容器板的厚度允许使用常规技术进行掺杂，并且硅化以改善RC常数。

2. 发明授权

US5566044A Base capacitor coupled photosensor with emitter tunnel oxide for very wide dynamic range in a contactless imaging array 失效
标题翻译：基极电容耦合光电传感器与发射极隧道氧化物，用于非接触式成像阵列中的非常宽的动态范围
公开(公告)号：US5566044A
公开(公告)日：1996-10-15
申请号：US438549
申请日：1995-05-10
申请人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
发明人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
IPC分类号： H01L27/146 , H01L31/11 , H01G4/06 , H01L23/58 , H01L31/062 , H01L31/18
CPC分类号： H01L31/1105 , H01L27/14681
摘要： A technique for decreasing the effective gain of a bipolar phototransistor at high light levels makes the image usable over a greatly extended range of illumination conditions. The effective current gain at high light levels is reduced by fabricating a "non-ideal" emitter, such as by inserting a thin 20 521 tunnel oxide between the emitter and base junction. The tunnel oxide between the emitter and base serves as a variable resistor as well as a good junction for carrier injection from the emitter. The total base voltage is the sum of the oxide voltage and the intrinsic base voltage. At high image intensity, the bipolar phototransistor will gradually enter into the saturation mode, i.e., the base to collector junction is forward biased. The beta is thus reduced. The bias of the collector should be about 0.3-0.8 V higher than the emitter at the 20.ANG. tunnel oxide thickness for optimum operation.
摘要翻译：降低双极光电晶体管在高光照条件下的有效增益的技术使得图像在大范围的照明条件下可用。通过制造“非理想”发射器，例如通过在发射极和基极结之间插入薄的20 521隧道氧化物，可以降低高光级的有效电流增益。发射极和基极之间的隧道氧化物用作可变电阻器，以及用于从发射极注入载流子的良好结。总基极电压是氧化物电压和本征基极电压之和。在高图像强度下，双极光电晶体管将逐渐进入饱和模式，即基极到集电极结正向偏置。因此，beta被减少了。在20 ANGSTROM隧道氧化物厚度下，集电极的偏压应比发射极高0.3-0.8V，以获得最佳的操作。

3. 发明授权

US5837574A Method of manufacturing a thin poly, capacitor coupled contactless imager with high resolution and wide dynamic range 失效
标题翻译：制造具有高分辨率和宽动态范围的薄型多电容耦合非接触式成像仪的方法
公开(公告)号：US5837574A
公开(公告)日：1998-11-17
申请号：US789397
申请日：1997-01-29
申请人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
发明人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/146 , H01L21/8242
CPC分类号： H01L27/14609 , H01L21/823406 , H01L21/8238 , Y10S148/01 , Y10S148/124
摘要： A capacitor coupled contactless imager structure and method of manufacturing the structure results in a phototransistor that includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the imager phototransistor. Silicon dioxide separates the polysilicon emitter contact and exposed surfaces of the base region from a layer of poly2 about 500-600 .ANG. thick that is formed to cover the entire base region.
摘要翻译：电容耦合的非接触式成像器结构及其结构的制造方法产生包含在P型半导体材料中形成的N型集电极区域的光电晶体管。在集电区域形成P型基极区域。形成与P型基极区域的表面接触的n掺杂多晶硅发射极接触，使得在基极区域中形成n +外延区域作为成像器光电晶体管的发射极。二氧化硅将基底区域的多晶硅发射极接触和暴露的表面与形成为覆盖整个基极区域的聚合物厚度约为500-600埃的厚度分离。

4. 发明授权

US5587596A Single MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range 失效
标题翻译：单MOS晶体管有源像素传感器单元具有自动防起霜和宽动态范围
公开(公告)号：US5587596A
公开(公告)日：1996-12-24
申请号：US531582
申请日：1995-09-20
申请人： Min-Hwa Chi , Albert Bergemont , Hosam Haggag
发明人： Min-Hwa Chi , Albert Bergemont , Hosam Haggag
IPC分类号： H01L27/146 , H01L31/062
CPC分类号： H01L27/14609 , H01L27/14656
摘要： The size of an active pixel sensor cell is reduced by utilizing a single MOS transistor formed in a well to perform the functions conventionally performed by a photogate/photodiode, a sense transistor, and an access transistor. Light energy striking the well varies the potential of the well which, in turn, varies the threshold voltage of the transistor. As a result, the current sourced by the transistor is proportional to the received light energy.
摘要翻译：有源像素传感器单元的尺寸通过利用形成在阱中的单个MOS晶体管来执行由光栅/光电二极管，感测晶体管和存取晶体管传统执行的功能来减小。冲击阱的光能改变了阱的电位，而这又影响了晶体管的阈值电压。结果，由晶体管产生的电流与所接收的光能成比例。

5. 发明授权

US5552619A Capacitor coupled contactless imager with high resolution and wide dynamic range 失效
标题翻译：电容耦合非接触式成像仪具有高分辨率和宽动态范围
公开(公告)号：US5552619A
公开(公告)日：1996-09-03
申请号：US436181
申请日：1995-05-10
申请人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
发明人： Albert Bergemont , Carver A. Mead , Min-hwa Chi , Hosam Haggag
IPC分类号： H01L27/105 , H01L27/146 , H01L31/11 , H01L31/06
CPC分类号： H01L31/1105 , H01L27/105 , Y10S148/124
摘要： A capacitor coupled contactless imager structure and a method of manufacturing the structure results is a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface to the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter contact and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.
摘要翻译：电容耦合非接触式成像器结构及其结构制造方法是一种光电晶体管，其结构包括形成在P型半导体材料中的N型集电极区域。在集电区域形成P型基极区域。形成与P型基极区域的表面接触的n掺杂多晶硅发射极触点，使得在基极区域中形成n +外延区域作为光电晶体管的发射极。二氧化硅将poly1发射极接触和暴露在基部区域的表面与部分覆盖基极区域的约3000-4000厚的poly2层分离; CMOS外围器件的栅极也是poly2。基极区域上的poly2用作成像器结构的基极耦合电容器和行导体。 poly2电容器板的厚度允许使用常规技术进行掺杂，并且硅化以改善RC常数。

6. 发明授权

US5932873A Capacitor-coupled bipolar active pixel sensor with integrated electronic shutter 失效
标题翻译：具有集成电子快门的电容耦合双极型有源像素传感器
公开(公告)号：US5932873A
公开(公告)日：1999-08-03
申请号：US932272
申请日：1997-09-17
申请人： Albert Bergemont , Min-Hwa Chi , Hosam Haggag , Carver Mead
发明人： Albert Bergemont , Min-Hwa Chi , Hosam Haggag , Carver Mead
IPC分类号： H01L27/146 , H01L31/11 , H01L21/00
CPC分类号： H01L31/1105 , H01L27/14681
摘要： A capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the "shutter") which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.
摘要翻译：具有集成电子快门的电容器耦合双极光电晶体管，用于减少与强图像成像有关的溢出和开花问题。通过使用用于去除多余图像产生的电荷的第二发射器（“快门”）来获得溢流控制和防喷射机制。这样就可以防止在光电晶体管暴露于强影像时图像积分期间基极 - 发射极结电位变得正向偏置。快门被偏置成比光电晶体管的第一发射极略低，以便当成像元件暴露于强影像时，基极 - 快门结点比基极 - 发射极结更早地向前偏置。所产生的孔的溢流电流然后被排放到快门，而不是进入发射器，在那里它会在列感测线上产生噪声。

7. 发明授权

US06215698B1 Flash eprom with byte-wide erasure 有权
标题翻译：闪存eprom与字节宽擦除
公开(公告)号：US06215698B1
公开(公告)日：2001-04-10
申请号：US09580711
申请日：2000-05-30
申请人： Hosam Haggag , Albert Bergemont
发明人： Hosam Haggag , Albert Bergemont
IPC分类号： G11C1604
CPC分类号： G11C16/16
摘要： Bytes of cells in a Flash electrically-programmable read-only-memory (EPROM) are individually erasable by breaking each row of memory cells into byte-wide segments of memory cells, and utilizing a source access transistor with each segment of memory cells to control the source voltage on each segment of memory cells.
摘要翻译：闪存电可编程只读存储器（EPROM）中的单元的字节可以通过将每行存储器单元分成存储器单元的字节宽段来单独地擦除，并且利用每个存储器单元段的源存取晶体管来控制存储器单元的每个段上的源电压。

8. 发明授权

US07903465B2 Memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的存储器阵列
公开(公告)号：US07903465B2
公开(公告)日：2011-03-08
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

9. 发明授权

US08325522B2 Memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的存储器阵列
公开(公告)号：US08325522B2
公开(公告)日：2012-12-04
申请号：US13012361
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

10. 发明申请

US20080266959A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖帽的不挥发性记忆细胞的记忆阵列
公开(公告)号：US20080266959A1
公开(公告)日：2008-10-30
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

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