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1. 发明授权

US08569896B2 Active area bonding compatible high current structures 有权
公开(公告)号：US08569896B2
公开(公告)日：2013-10-29
申请号：US13532843
申请日：2012-06-26
申请人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert Lomenick , Chris A. McCarty
发明人： John T. Gasner , Michael D. Church , Sameer D. Parab , Paul E. Bakeman, Jr. , David A. Decrosta , Robert Lomenick , Chris A. McCarty
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76801 , H01L21/32051 , H01L21/76829 , H01L21/76841 , H01L21/7685 , H01L21/76886 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/48 , H01L24/81 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/04941 , H01L2924/14 , H01L2224/45099
摘要： A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer.

2. 发明授权

US08325522B2 Memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的存储器阵列
公开(公告)号：US08325522B2
公开(公告)日：2012-12-04
申请号：US13012361
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

3. 发明申请

US20080266959A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖帽的不挥发性记忆细胞的记忆阵列
公开(公告)号：US20080266959A1
公开(公告)日：2008-10-30
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

4. 发明授权

US08345488B2 Flash memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的闪存阵列
公开(公告)号：US08345488B2
公开(公告)日：2013-01-01
申请号：US13080814
申请日：2011-04-06
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

5. 发明授权

US08320180B2 Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general purpose CMOS technology with thick gate oxide 有权
标题翻译：多时间可编程（MTP）PMOS浮动栅极非易失性存储器件，用于具有厚栅极氧化物的通用CMOS技术
公开(公告)号：US08320180B2
公开(公告)日：2012-11-27
申请号：US13077065
申请日：2011-03-31
申请人： Alexander Kalnitsky , Michael D. Church
发明人： Alexander Kalnitsky , Michael D. Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.
摘要翻译：根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的延伸漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。浮置栅极PMOS晶体管可以存储逻辑状态。可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

6. 发明授权

US08315100B2 Memory array of floating gate-based non-volatile memory cells 有权
公开(公告)号：US08315100B2
公开(公告)日：2012-11-20
申请号：US13012381
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/06 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

7. 发明申请

US20120289041A1 BALLASTED POLYCRYSTALLINE FUSE 有权
标题翻译：阻挡多晶硅保险丝
公开(公告)号：US20120289041A1
公开(公告)日：2012-11-15
申请号：US13356263
申请日：2012-01-23
申请人： Michael D. Church
发明人： Michael D. Church
IPC分类号： H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.
摘要翻译：多晶熔丝包括在衬底上的第一层多晶材料和在第一层上的第二层硅化物材料。第一和第二层被成形为形成第一宽度的第一和第二端部，该第一和第二端部沿熔丝的长度通过比第一宽度窄的第二宽度的熔丝部分接合。第一和第二触点分别连接到第一和第二端子部分。所述硅化物材料沿所述熔丝的长度在所述第二层的末端区域不连续。

8. 发明申请

US20120261767A1 METHOD AND STRUCTURE FOR REDUCING GATE LEAKAGE CURRENT AND POSITIVE BIAS TEMPERATURE INSTABILITY DRIFT 审中-公开
标题翻译：减少闸门泄漏电流的方法和结构和正偏压温度不稳定性
公开(公告)号：US20120261767A1
公开(公告)日：2012-10-18
申请号：US13423841
申请日：2012-03-19
申请人： Michael D. Church
发明人： Michael D. Church
IPC分类号： H01L27/088 , H01L27/02 , H01L21/3105 , H01L21/314 , H01L21/311
CPC分类号： H01L21/823456 , H01L21/823443 , H01L21/823462 , H01L21/823475 , H01L21/823481 , H01L27/088
摘要： Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.
摘要翻译：提供了减少栅极漏电流和正偏压温度不稳定性漂移的系统和方法。在一个实施例中，系统包括半导体衬底上的p沟道场效应晶体管（PFET）器件和衬底上的高压晶体管。该系统还包括在衬底中形成的多个硅化物，在PFET器件和高压晶体管附近形成多个硅化物。此外，该系统包括形成在衬底上的缓冲氧化物层，PFET器件和高压晶体管，以及形成在缓冲层上的防潮层，由氮氧化硅组成的防潮层。此外，该系统包括形成在湿气屏障上的层间电介质器件和延伸穿过层间电介质，湿气屏障和缓冲氧化物层的多个电触点，其中多个电触头电连接到多个硅化物。

9. 发明授权

US08218370B2 Memory array of floating gate-based non-volatile memory cells 有权
公开(公告)号：US08218370B2
公开(公告)日：2012-07-10
申请号：US13012368
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/14 , G11C16/10 , G11C16/08 , G11C16/24 , G11C16/06 , G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

10. 发明申请

US20110272756A1 METHOD OF FORMING AN INSULATOR LAYER IN A SEMICONDUCTOR STRUCTURE AND STRUCTURES RESULTING THEREFROM 有权
标题翻译：在半导体结构中形成绝缘体层的方法和结果
公开(公告)号：US20110272756A1
公开(公告)日：2011-11-10
申请号：US12942516
申请日：2010-11-09
申请人： Michael D. Church
发明人： Michael D. Church
IPC分类号： H01L27/092 , H01L29/772 , H01L21/8238 , H01L21/02 , H01L21/762
CPC分类号： H01L21/823462 , H01L21/823468 , H01L27/0629 , H01L27/0805 , H01L27/088
摘要： An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.
摘要翻译：公开了电子系统，半导体结构的制造方法和一个或多个半导体结构。例如，公开了一种制造半导体结构的方法，其包括在半导体衬底上形成第一半导体子结构，在第一半导体子结构和半导体衬底之上形成第一间隔层，并至少形成第二半导体子结构第一间隔层的一部分。

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