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1. 发明授权

US5466626A Micro mask comprising agglomerated material 失效
标题翻译：包含凝聚材料的微型掩模
公开(公告)号：US5466626A
公开(公告)日：1995-11-14
申请号：US168703
申请日：1993-12-16
申请人： Michael Armacost , A. Richard Baker, Jr. , Wayne S. Berry , Daniel A. Carl , Donald M. Kenney , Thomas J. Licata
发明人： Michael Armacost , A. Richard Baker, Jr. , Wayne S. Berry , Daniel A. Carl , Donald M. Kenney , Thomas J. Licata
IPC分类号： H01L21/02 , H01L21/033 , H01L21/8242
CPC分类号： H01L28/92 , B82Y10/00 , H01L21/0332 , H01L21/0338 , H01L27/1085 , H01L27/10852 , H01L28/84 , Y10S148/105 , Y10S438/947 , Y10S438/964 , Y10S977/81 , Y10S977/888
摘要： The subject invention provides a method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.
摘要翻译：本发明提供一种在诸如电容器的衬底中形成凹槽的方法，以增加其表面积，从而增加电容器的电荷存储容量。这是通过利用在基板的表面上通过附聚形成的微掩模来实现的。将聚集的材料，例如金，氮化钛或硅化钛用作掩模，用于选择性地蚀刻基板以在其中形成凹部。或者，氧化物转移掩模可以与聚集的材料微掩模一起使用以蚀刻基底。

2. 发明授权

US5672537A Method for preparing a narrow angle defined trench in a substrate 失效
标题翻译：在衬底中制备窄角限定沟槽的方法
公开(公告)号：US5672537A
公开(公告)日：1997-09-30
申请号：US714276
申请日：1996-09-17
申请人： Daniel A. Carl , Donald M. Kenney , Walter E. Mlynko , Son Van Nguyen
发明人： Daniel A. Carl , Donald M. Kenney , Walter E. Mlynko , Son Van Nguyen
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/763 , H01L21/8242 , H01L27/108 , H01L21/76
CPC分类号： H01L27/10861 , H01L21/763 , Y10S148/05
摘要： Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam. The polysilicon (20) in the trench (21) may be in the shape of a solid angled block approximating the shadow line from the top of side wall (26) to side wall (27); however, it is preferred that the polysilicon take the form of a conformal layer in trench (21) prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon (20) using strap (23) that electrically connects the side wall (26) with the polysilicon (20). Strap (23) is sized such that it does not extend to the opposite side wall (27) of trench (21), thereby avoiding short circuits. Having the polysilicon (20) approximate the shadow line of the etch permits narrowing the distance between adjacent straps (23) and (24) in an array without the risk of creating a short circuit.
摘要翻译：在沟槽（21）中的多晶硅（20）以一定角度蚀刻，以在沟槽内产生具有接近距离光束源的沟槽（21）的侧壁（26）的阴影的形状特征的导体。具体地说，当第一侧壁（26）最靠近光束源和第二侧壁（27）离光束源最远时，第一侧壁（26）上的多晶硅几乎与第一侧壁（而更暴露的侧壁（27）上的多晶硅比第一侧壁（26）低得多，并且相对于光束近似于第二侧壁（27）上的第一侧壁（26）的阴影。沟槽（21）中的多晶硅（20）可以是从侧壁（26）的顶部到侧壁（27）近似阴影线的实心角块的形状; 然而，优选的是，多晶硅在蚀刻之前在沟槽（21）中具有保形层的形式，使得多晶硅最终具有接近阴影线的成角度的“U”形。使用将侧壁（26）与多晶硅（20）电连接的带（23）与多晶硅（20）接触。带（23）的尺寸使得其不延伸到沟槽（21）的相对侧壁（27），从而避免短路。使多晶硅（20）近似于蚀刻线的阴影线允许在阵列中使相邻带（23）和（24）之间的距离变窄，而不会产生短路。

3. 发明授权

US5610441A Angle defined trench conductor for a semiconductor device 失效
标题翻译：用于半导体器件的角度定义的沟槽导体
公开(公告)号：US5610441A
公开(公告)日：1997-03-11
申请号：US444465
申请日：1995-05-19
申请人： Daniel A. Carl , Donald M. Kenney , Walter E. Mlynko , Son V. Nguyen
发明人： Daniel A. Carl , Donald M. Kenney , Walter E. Mlynko , Son V. Nguyen
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/763 , H01L21/8242 , H01L27/108 , H01L23/18 , H01L23/52
CPC分类号： H01L27/10861 , H01L21/763 , Y10S148/05
摘要： Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon using strap that electrically connects the side wall with the polysilicon. Strap is sized such that it does not extend to the opposite side wall of trench, thereby avoiding short circuits. Having the polysilicon approximate the shadow line of the etch permits narrowing the distance between adjacent straps and in an array without the risk of creating a short.
摘要翻译：在沟槽中蚀刻多晶硅以在沟槽内产生导体，该导体具有接近最接近光束源的沟槽侧壁阴影的形状特征。具体地，当第一侧壁最靠近光束源并且第二侧壁距离光束源最远时，第一侧壁上的多晶硅几乎与第一侧壁一样高，而在较大曝光侧的多晶硅壁比第一侧壁大得多，并且近似于相对于梁的第二侧壁上的第一侧壁的阴影。沟槽中的多晶硅可以是接近从侧壁顶部到侧壁上的阴影线的阴影线的实心角形块的形状，然而，优选地，多晶硅在沟槽中具有保形层的形式以蚀刻，使得多晶硅最终具有近似于阴影线的成角度“U”形。使用将侧壁与多晶硅电连接的带子与多晶硅接触。带的尺寸使得其不延伸到沟槽的相对侧壁，从而避免短路。使多晶硅近似于蚀刻的阴影线允许在相邻带之间和阵列之间的距离变窄，而不会产生短路。

4. 发明授权

US06884724B2 Method for dishing reduction and feature passivation in polishing processes 失效
公开(公告)号：US06884724B2
公开(公告)日：2005-04-26
申请号：US09939323
申请日：2001-08-24
申请人： Wei-Yung Hsu , Liang-Yuh Chen , Ratson Morad , Daniel A. Carl
发明人： Wei-Yung Hsu , Liang-Yuh Chen , Ratson Morad , Daniel A. Carl
IPC分类号： H01L21/288 , H01L21/321 , H01L21/20
CPC分类号： H01L21/7684 , H01L21/3212
摘要： Methods and apparatus for planarizing a substrate surface are provided. In one aspect, a method is provided for planarizing a substrate surface including polishing a first conductive material to a barrier layer material, depositing a second conductive material on the first conductive material by an electrochemical deposition technique, and polishing the second conductive material and the barrier layer material to a dielectric layer. In another aspect, a processing system is provided for forming a planarized layer on a substrate, the processing system including a computer based controller configured to cause the system to polish a first conductive material to a barrier layer material, deposit a second conductive material on the first conductive material by an electrochemical deposition technique, and polish the second conductive material and the barrier layer material to a dielectric layer.

5. 发明授权

US06436267B1 Method for achieving copper fill of high aspect ratio interconnect features 有权
标题翻译：实现高宽比互连特征铜填充的方法
公开(公告)号：US06436267B1
公开(公告)日：2002-08-20
申请号：US09650108
申请日：2000-08-29
申请人： Daniel A. Carl , Barry Chin , Liang Chen , Robin Cheung , Peijun Ding , Yezdi Dordi , Imran Hashim , Peter Hey , Ashok K. Sinha
发明人： Daniel A. Carl , Barry Chin , Liang Chen , Robin Cheung , Peijun Ding , Yezdi Dordi , Imran Hashim , Peter Hey , Ashok K. Sinha
IPC分类号： C23C2802
CPC分类号： H01L21/2885 , H01L21/76877
摘要： One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.
摘要翻译：本发明的一个方面提供一致的金属电镀技术，以在半导体衬底上形成亚微米高纵横比特征的无空隙金属互连。本发明的一个实施方案提供了一种用于在基底上填充亚微米特征的方法，包括反应性预清洗基底，使用高密度等离子体物理气相沉积在基底上沉积阻挡层; 使用高密度等离子体物理气相沉积在阻挡层上沉积种子层; 以及使用高电阻电解质电化学沉积金属，并且在第一周期期间在第一沉积期间施加第一电流密度，然后施加第二电流密度。

6. 发明授权

US07427568B2 Method of forming an interconnect structure 失效
标题翻译：形成互连结构的方法
公开(公告)号：US07427568B2
公开(公告)日：2008-09-23
申请号：US11424359
申请日：2006-06-15
申请人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
IPC分类号： H01L21/311 , C23C14/34
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

7. 发明授权

US07137879B2 Conductive polishing article for electrochemical mechanical polishing 有权
公开(公告)号：US07137879B2
公开(公告)日：2006-11-21
申请号：US11393220
申请日：2006-03-30
申请人： Liang-Yuh Chen , Yuchun Wang , Yan Wang , Alain Duboust , Daniel A. Carl , Ralph Wadensweiler , Manoocher Birang , Paul D. Butterfield , Rashid Mavliev , Stan D. Tsai
发明人： Liang-Yuh Chen , Yuchun Wang , Yan Wang , Alain Duboust , Daniel A. Carl , Ralph Wadensweiler , Manoocher Birang , Paul D. Butterfield , Rashid Mavliev , Stan D. Tsai
IPC分类号： B24D3/34 , B24D11/00 , B24D17/00
CPC分类号： B82Y30/00 , B24B37/046 , B24B37/24 , B24B37/26 , B24D3/34
摘要： An article of manufacture and apparatus are provided for planarizing a substrate surface. In one aspect, an article of manufacture is provided for polishing a substrate including polishing article comprising a body having at least a partially conductive surface adapted to polish the substrate and a mounting surface. A plurality of perforations may be formed in the polishing article for flow of material therethrough. In another aspect, a polishing article for polishing a substrate includes a body having a polishing surface and a conductive element disposed therein. The conductive element may have a contact surface that extends beyond a plane defined by the polishing surface. The polishing surface may have one or more pockets formed therein. The conductive element may be disposed in each of the polishing pockets.

8. 发明授权

US07115516B2 Method of depositing a material layer 失效
标题翻译：沉积材料层的方法
公开(公告)号：US07115516B2
公开(公告)日：2006-10-03
申请号：US09974535
申请日：2001-10-09
申请人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
IPC分类号： H01L21/4763
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

9. 发明授权

US06258223B1 In-situ electroless copper seed layer enhancement in an electroplating system 有权
标题翻译：电镀系统中的原位无电铜种子层增强
公开(公告)号：US06258223B1
公开(公告)日：2001-07-10
申请号：US09350877
申请日：1999-07-09
申请人： Robin Cheung , Daniel A. Carl , Yezdi Dordi , Peter Hey , Ratson Morad , Liang-Yuh Chen , Paul F. Smith , Ashok K. Sinha
发明人： Robin Cheung , Daniel A. Carl , Yezdi Dordi , Peter Hey , Ratson Morad , Liang-Yuh Chen , Paul F. Smith , Ashok K. Sinha
IPC分类号： C25D1700
CPC分类号： H01L21/68721 , C25D7/123 , C25D17/001 , H01L21/68728 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a system that provides for electroless deposition performed in-situ with an electroplating process to minimize oxidation and other contaminants prior to the electroplating process. The system allows the substrate to be transferred from the electroless deposition process to the electroplating process with a protective coating to also minimize oxidation. The system generally includes a mainframe having a mainframe substrate transfer robot, a loading station disposed in connection with the mainframe, one or more processing facilities disposed in connection with the mainframe, an electroless supply fluidly connected to the one or more processing applicators and optionally includes a spin-rinse-dry (SRD) station, a rapid thermal anneal chamber and a system controller for controlling the deposition processes and the components of the electro-chemical deposition system.
摘要翻译：本发明公开了一种系统，其提供用电镀方法原位进行的无电沉积，以在电镀过程之前使氧化和其它污染物最小化。该系统允许基板由无电镀沉积工艺转移到具有保护涂层的电镀工艺中以使氧化最小化。该系统通常包括具有主机基板传送机器人的主机，与主机连接设置的加载站，与主机连接设置的一个或多个处理设备，流体连接到该一个或多个处理施加器的无电解供应器，并且可选地包括旋转干燥（SRD）站，快速热退火室和用于控制沉积过程和电化学沉积系统的组件的系统控制器。

10. 发明授权

US07772121B2 Method of forming a trench structure 失效
标题翻译：形成沟槽结构的方法
公开(公告)号：US07772121B2
公开(公告)日：2010-08-10
申请号：US11424351
申请日：2006-06-15
申请人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
发明人： Liang-Yuh Chen , Daniel A. Carl , Israel Beinglass
IPC分类号： H01L21/00
CPC分类号： C23C16/45589 , C23C14/046 , C23C16/045 , H01L21/2855 , H01L21/28556 , H01L21/76843 , H01L21/76865
摘要： A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
摘要翻译：公开了一种在具有高纵横比特征的基底上形成层的方法。该层由包含一种或多种工艺气体和一种或多种蚀刻物质的气体混合物形成。一种或多种工艺气体反应以在衬底上沉积材料层。结合材料层沉积，蚀刻物质选择性地去除与高纵横比特征开口相邻的沉积材料层的部分，以无空隙和/或无缝隙的方式填充这些特征。材料层可以使用物理气相沉积（PVD）和/或化学气相沉积（CVD）技术沉积在衬底上。

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