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1. 发明授权

US5610441A Angle defined trench conductor for a semiconductor device 失效
标题翻译：用于半导体器件的角度定义的沟槽导体
公开(公告)号：US5610441A
公开(公告)日：1997-03-11
申请号：US444465
申请日：1995-05-19
申请人： Daniel A. Carl , Donald M. Kenney , Walter E. Mlynko , Son V. Nguyen
发明人： Daniel A. Carl , Donald M. Kenney , Walter E. Mlynko , Son V. Nguyen
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/763 , H01L21/8242 , H01L27/108 , H01L23/18 , H01L23/52
CPC分类号： H01L27/10861 , H01L21/763 , Y10S148/05
摘要： Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon using strap that electrically connects the side wall with the polysilicon. Strap is sized such that it does not extend to the opposite side wall of trench, thereby avoiding short circuits. Having the polysilicon approximate the shadow line of the etch permits narrowing the distance between adjacent straps and in an array without the risk of creating a short.
摘要翻译：在沟槽中蚀刻多晶硅以在沟槽内产生导体，该导体具有接近最接近光束源的沟槽侧壁阴影的形状特征。具体地，当第一侧壁最靠近光束源并且第二侧壁距离光束源最远时，第一侧壁上的多晶硅几乎与第一侧壁一样高，而在较大曝光侧的多晶硅壁比第一侧壁大得多，并且近似于相对于梁的第二侧壁上的第一侧壁的阴影。沟槽中的多晶硅可以是接近从侧壁顶部到侧壁上的阴影线的阴影线的实心角形块的形状，然而，优选地，多晶硅在沟槽中具有保形层的形式以蚀刻，使得多晶硅最终具有近似于阴影线的成角度“U”形。使用将侧壁与多晶硅电连接的带子与多晶硅接触。带的尺寸使得其不延伸到沟槽的相对侧壁，从而避免短路。使多晶硅近似于蚀刻的阴影线允许在相邻带之间和阵列之间的距离变窄，而不会产生短路。

2. 发明授权

US5412246A Low temperature plasma oxidation process 失效
标题翻译：低温等离子体氧化工艺
公开(公告)号：US5412246A
公开(公告)日：1995-05-02
申请号：US186568
申请日：1994-01-26
申请人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
发明人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
IPC分类号： C23C8/36 , H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8242 , H01L27/108 , H01L29/12
CPC分类号： H01L21/32105 , H01L21/02238 , H01L21/02252 , H01L21/31662 , Y10S148/118 , Y10S257/90
摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (
摘要翻译：一种在半导体器件的表面上形成薄膜的工艺。该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1，在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

3. 发明申请

US20130333923A1 MODULATED COMPOSITIONAL AND STRESS CONTROLLED MULTILAYER ULTRATHIN CONFORMAL SiNx DIELECTRICS USED IN NANO DEVICE FABRICATION 审中-公开
标题翻译：在纳米器件制造中使用的调制组合和应力控制的多层超大规模SiNx电介质
公开(公告)号：US20130333923A1
公开(公告)日：2013-12-19
申请号：US13495545
申请日：2012-06-13
申请人： Mihaela Balseanu , Stephan A. Cohen , Alfred Grill , Thomas J. Haigh, JR. , Son V. Nguyen , Mei-Yee Shek , Hosadurga Shobha , Li-Qun Xia
发明人： Mihaela Balseanu , Stephan A. Cohen , Alfred Grill , Thomas J. Haigh, JR. , Son V. Nguyen , Mei-Yee Shek , Hosadurga Shobha , Li-Qun Xia
IPC分类号： C23C16/34 , H05K1/02
CPC分类号： C23C16/345 , C23C16/56 , H01L21/4803 , H05K1/0298 , Y10T428/24975
摘要： A layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers is deposited on a substrate. A plasma nitridation process is carried out on the layer. These steps are repeated for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained. Such steps can be used to provide a multilayer silicon nitride dielectric formed on a substrate having an upper surface of dielectric material with Cu and other conductors embedded within, and a plurality of steps. The multilayer silicon nitride dielectric has a plurality of individual layers each having a thickness from 0.5 nanometers to 2.4 nanometers, and the multilayer silicon nitride dielectric conformally covers the steps of the substrate with a conformality of at least seventy percent. A multilayer silicon nitride dielectric, and a multilevel back end of line interconnect wiring structure using same, are also provided.
摘要翻译：将厚度为0.5纳米至2.4纳米的氮化硅层沉积在基底上。在层上进行等离子体氮化处理。对于多个附加氮化硅层重复这些步骤，直到达到预定厚度。可以使用这样的步骤来提供形成在具有介电材料的上表面的衬底上的多层氮化硅电介质，其中Cu和其它导体嵌入其中并且多个步骤。多层氮化硅电介质具有各自具有0.5纳米至2.4纳米厚度的多个单独层，多层氮化硅电介质保形地覆盖具有至少百分之七十的保形度的基底的步骤。还提供了多层氮化硅电介质，以及使用该多层氮化硅电介质的多层后端的布线结构。

4. 发明申请

US20130043514A1 MULTIPHASE ULTRA LOW K DIELECTRIC MATERIAL 有权
标题翻译：多相超低K电介质材料
公开(公告)号：US20130043514A1
公开(公告)日：2013-02-21
申请号：US13214157
申请日：2011-08-19
申请人： Alfred Grill , Thomas J. Haigh, JR. , Kelly Malone , Son V. Nguyen , Vishnubhai V. Patel , Hosadurga Shobha
发明人： Alfred Grill , Thomas J. Haigh, JR. , Kelly Malone , Son V. Nguyen , Vishnubhai V. Patel , Hosadurga Shobha
IPC分类号： H01L29/78 , H01L23/48 , C08J9/26 , H01L21/31
CPC分类号： H01L29/511 , C08J9/26 , C08J2201/042 , C08J2383/04 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02337 , H01L21/02348 , H01L21/02351 , H01L21/76801 , H01L21/76825 , H01L21/76829 , H01L21/76832 , H01L23/5329 , H01L29/515 , H01L2924/0002 , H01L2924/00
摘要： A multiphase ultra low k dielectric process incorporating an organo-silicon precursor including an organic porogen, high frequency radio frequency power just above plasma initiation in a PECVD chamber and energy post treatment. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa. A graded carbon adhesion layer of SiO2 and porous SiCOH.
摘要翻译：包含有机硅前驱体的多相超低k电介质工艺，其包括有机致孔剂，在PECVD腔室中等离子体起始之前的高频射频功率和能量后处理。具有k小于2.7且弹性模量大于7GPa的多孔SiCOH电介质材料。 SiO2和多孔SiCOH的分级碳粘附层。

5. 发明授权

US08362596B2 Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same 有权
标题翻译：具有压缩应力的工程互连电介质盖和包含它们的互连结构
公开(公告)号：US08362596B2
公开(公告)日：2013-01-29
申请号：US12502690
申请日：2009-07-14
申请人： Stephan A. Cohen , Alfred Grill , Thomas J. Haigh, Jr. , Xiao H. Liu , Son V. Nguyen , Thomas M. Shaw , Hosadurga Shobha
发明人： Stephan A. Cohen , Alfred Grill , Thomas J. Haigh, Jr. , Xiao H. Liu , Son V. Nguyen , Thomas M. Shaw , Hosadurga Shobha
IPC分类号： H01L23/58 , H01L21/302
CPC分类号： H01L23/5329 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.
摘要翻译：提供具有小于4.2的介电常数的介电覆盖层，与传统的介电覆盖层相比，其对UV和/或E-Beam辐射具有更高的机械和电学稳定性。此外，介电覆盖层在沉积后处理时保持一致的压应力。电介质覆盖层包括三层介电材料，其中至少一层具有良好的抗氧化性，耐导电性金属扩散，并且在至少UV固化下表现出高机械稳定性。低k电介质封盖层还包括含有电子给体和双键电子的氮含量层。低k电介质覆盖层还具有高压缩应力和高模量，并且在后沉积固化处理中是稳定的，这导致较少的膜和器件开裂和改进的器件可靠性。

6. 发明授权

US6057250A Low temperature reflow dielectric-fluorinated BPSG 失效
标题翻译：低温回流电介质氟化BPSG
公开(公告)号：US6057250A
公开(公告)日：2000-05-02
申请号：US14431
申请日：1998-01-27
申请人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
发明人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
IPC分类号： H01L21/31 , C23C16/40 , H01L21/316 , H01L21/225 , H01L21/469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02131 , H01L21/02211 , H01L21/31625 , H01L21/31629
摘要： An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface. A F-BPSG glass and semiconductor wafers having a layer of fluorine doped BPSG thereon formed by the method and apparatus of the invention are also provided.
摘要翻译：提供了一种用于在半导体器件上使用低压化学气相沉积工艺形成氟掺杂硼磷硅酸（F-BPSG）玻璃的装置和方法。 F-BPSG玻璃在基板上表现出基本上无空隙和无颗粒的层，其结构具有窄至0.10微米的间隙，纵横比为6:1。反应物气体包括硼和磷掺杂剂的源，氧和TEOS和FTES的混合物。在低压CVD工艺中使用TEOS和FTES的混合物提供具有上述增强特性的F-BPSG层。本发明的优选方法是在约750-850℃的温度和1至3托的压力下进行沉积，以在沉积过程中提供F-BPSG的原位回流。在相同的化学气相沉积室中的相似条件下还优选退火以进一步平坦化F-BPSG表面。还提供了通过本发明的方法和装置形成的具有氟掺杂BPSG层的F-BPSG玻璃和半导体晶片。

7. 发明授权

US5538592A Non-random sub-lithography vertical stack capacitor 失效
标题翻译：非随机子光刻垂直堆叠电容器
公开(公告)号：US5538592A
公开(公告)日：1996-07-23
申请号：US279607
申请日：1994-07-22
申请人： Bomy A. Chen , Gary B. Bronner , Son V. Nguyen
发明人： Bomy A. Chen , Gary B. Bronner , Son V. Nguyen
IPC分类号： H01L27/04 , H01L21/02 , H01L21/306 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40 , Y10S438/947
摘要： Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.
摘要翻译：亚光刻尺寸的集成电路结构通过在待蚀刻材料体上的孔内的不同蚀刻速率的交替层材料的共形沉积形成。然后选择性地和优先地蚀刻交替层中的材料之一以形成掩模，通过该掩模可以对要蚀刻的材料的主体进行蚀刻。该技术特别适用于形成用于存储器单元的结构上坚固的电容器，其大大增加了板面积，导致增加的电容，同时保持了电容器结构的小的占地面积。

8. 发明授权

US5204138A Plasma enhanced CVD process for fluorinated silicon nitride films 失效
标题翻译：氟化氮化硅膜的等离子体增强CVD工艺
公开(公告)号：US5204138A
公开(公告)日：1993-04-20
申请号：US814973
申请日：1991-12-24
申请人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
发明人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
IPC分类号： C23C14/06 , C23C16/34 , C23C16/505 , C30B25/02 , H01L21/318
CPC分类号： C23C16/505 , C23C16/345
摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride layer on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4.
摘要翻译：公开了一种用于在衬底上制造氟化氮化硅层的等离子体增强化学气相沉积工艺。该方法利用硅烷，全氟硅烷和氮气的混合物来制备具有高共形性和稳定性的膜。混合物中的硅烷和全氟硅烷的体积比为0.05-1。优选的硅烷是SiH 4，优选的全氟硅烷是SiF 4。

9. 发明授权

US4635139A Asperity burst writer 失效
标题翻译：不明朗的作家
公开(公告)号：US4635139A
公开(公告)日：1987-01-06
申请号：US769276
申请日：1985-08-26
申请人： Son V. Nguyen , James M. Severson
发明人： Son V. Nguyen , James M. Severson
IPC分类号： G11B27/36 , G11B33/10 , G11B5/02 , G05F1/00
CPC分类号： G11B33/10 , G11B27/36
摘要： A glide head is used to test a rigid magnetic disk surface for projecting asperities. Using a two rail head with the read/write transducer mounted at the rear of the rail at the side of the head toward which the head is being radially advanced and skewing the head so that the trailing edge of the head approaches each track before the leading edge as the head is advanced, it is possible to write a pattern from a known position relative an event or asperity identified by a mechanical transducer associated with the head to the index location. Using a developer, it is then possible to readily identify the asperity during microscopic examination of the disk surface.
摘要翻译：滑动头用于测试刚性磁盘表面，用于突出凹凸。使用两轨头，其中读/写换能器安装在头部后方的导轨的后部，头部朝向头部径向前进并使头部倾斜，使得头部的后缘在前导线之前接近每个轨道当头部前进时，可以将相对于与头部相关联的机械传感器识别的事件或粗糙度的已知位置的图案写入索引位置。使用显影剂，可以容易地识别在盘表面的显微镜检查期间的凹凸。

10. 发明授权

US09241792B2 Two-step heart valve implantation 有权
标题翻译：两步心脏瓣膜植入
公开(公告)号：US09241792B2
公开(公告)日：2016-01-26
申请号：US12392995
申请日：2009-02-25
申请人： Netanel Benichou , Son V. Nguyen , Benjamin Spenser
发明人： Netanel Benichou , Son V. Nguyen , Benjamin Spenser
IPC分类号： A61F2/24
CPC分类号： A61F2/2418 , A61F2/2427 , A61F2/2433 , A61F2220/0008 , A61F2220/0016 , A61F2230/0054 , A61F2250/0059 , A61F2250/0063
摘要： A two-part implantable heart valve and procedure are disclosed that allow expansion and positioning of a first part of the implantable heart valve having a temporary or transient valvular structure. A second part of the implantable heart valve is deployed within the first part and attaches thereto. The valvular structure of the second part then acts to function as the heart valve replacement. A tool or system is provided for determining an adequate percutaneous heart valve size for a given stenotic valve. A balloon can be inflated inside the stenotic valve to a desired pressure. When this pressure is reached an angiographic image is taken and the balloon diameter is measured at a waist area created by contact between the balloon and the stenotic valve. The diameter represents the minimum percutaneous heart valve diameter to be implanted.
摘要翻译：公开了两部分可植入心脏瓣膜和程序，其允许具有临时或暂时瓣膜结构的可植入心脏瓣膜的第一部分的膨胀和定位。可植入心脏瓣膜的第二部分部署在第一部分内并且附接到其上。然后，第二部分的瓣膜结构起到充当心脏瓣膜置换作用。提供了一种用于确定给定狭窄瓣膜的足够的经皮心脏瓣膜尺寸的工具或系统。气囊可以在狭窄的瓣膜内充气到期望的压力。当达到该压力时，取出血管造影图像，并且在通过球囊和狭窄瓣膜之间的接触产生的腰部区域测量球囊直径。直径代表要植入的最小经皮心脏瓣膜直径。

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