专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080136500A1 CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS 有权
标题翻译：用于产生多个输出电压的充电泵
公开(公告)号：US20080136500A1
公开(公告)日：2008-06-12
申请号：US11608941
申请日：2006-12-11
申请人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
发明人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

2. 发明授权

US07579902B2 Charge pump for generation of multiple output-voltage levels 有权
标题翻译：用于产生多个输出电压电平的电荷泵
公开(公告)号：US07579902B2
公开(公告)日：2009-08-25
申请号：US11608941
申请日：2006-12-11
申请人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
发明人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

3. 发明授权

US07414891B2 Erase verify method for NAND-type flash memories 有权
标题翻译：擦除NAND型闪存的验证方法
公开(公告)号：US07414891B2
公开(公告)日：2008-08-19
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/00
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

4. 发明申请

US20080165585A1 ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES 有权
标题翻译：用于NAND型闪存存储器的擦除验证方法
公开(公告)号：US20080165585A1
公开(公告)日：2008-07-10
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

5. 发明授权

US07525856B2 Apparatus and method to manage external voltage for semiconductor memory testing with serial interface 有权
标题翻译：使用串行接口管理半导体存储器测试的外部电压的装置和方法
公开(公告)号：US07525856B2
公开(公告)日：2009-04-28
申请号：US11696521
申请日：2007-04-04
申请人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
发明人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
IPC分类号： G11C29/00
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
摘要翻译：串行接口闪存设备包括数据/地址I / O引脚和时钟输入引脚。双向缓冲器耦合到数据/地址I / O引脚。包括数据方向控制的串行接口逻辑块耦合到时钟引脚，双向缓冲器，内部控制逻辑以及读取电压和修改电压发生器。第一开关耦合到读电压发生器和时钟缓冲器，第二开关耦合到修改电压发生器和时钟缓冲器，第一和第二开关各自具有控制输入。存储器驱动器通过第一和第二开关耦合到读取电压发生器和修改电压发生器。第一和第二寄存器耦合在串行接口逻辑与第一和第二开关之间。存储器阵列耦合到存储器驱动器和读取放大器，并且程序缓冲器耦合在串行接口逻辑和存储器驱动器之间。

6. 发明申请

US20080246504A1 APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR MEMORY TESTING WITH SERIAL INTERFACE 有权
标题翻译：用于串行接口的半导体存储器测试管理外部电压的装置和方法
公开(公告)号：US20080246504A1
公开(公告)日：2008-10-09
申请号：US11696521
申请日：2007-04-04
申请人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
发明人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
IPC分类号： G01R31/00
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
摘要翻译：串行接口闪存设备包括数据/地址I / O引脚和时钟输入引脚。双向缓冲器耦合到数据/地址I / O引脚。包括数据方向控制的串行接口逻辑块耦合到时钟引脚，双向缓冲器，内部控制逻辑以及读取电压和修改电压发生器。第一开关耦合到读电压发生器和时钟缓冲器，第二开关耦合到修改电压发生器和时钟缓冲器，第一和第二开关各自具有控制输入。存储器驱动器通过第一和第二开关耦合到读取电压发生器和修改电压发生器。第一和第二寄存器耦合在串行接口逻辑与第一和第二开关之间。存储器阵列耦合到存储器驱动器和读取放大器，并且程序缓冲器耦合在串行接口逻辑和存储器驱动器之间。

7. 发明申请

US20130193590A1 SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：包括电压转换器电路的半导体器件及制造半导体器件的方法
公开(公告)号：US20130193590A1
公开(公告)日：2013-08-01
申请号：US13363242
申请日：2012-01-31
申请人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
发明人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
IPC分类号： H01L23/49 , H01L21/50
CPC分类号： H01L23/50 , G11C5/147 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48669 , H01L2224/49113 , H01L2224/73265 , H01L2224/85205 , H03K17/223 , H03K19/0013 , H01L2924/00014 , H01L2924/20752 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.
摘要翻译：半导体器件包括第一接合焊盘，第二接合焊盘，接合到第一和第二接合焊盘中的所选择的接合焊盘的引线，电连接到第一接合焊盘的电源线，以及耦合到第二接合焊盘的电压转换器电路当焊丝接合到第二焊盘上时，电压转换器电路被激活以产生与电压转换器电路通过电线和第二接合焊盘接收的电压不同的内部电源电压，并且提供内部当电线连接到第一接合焊盘以允许电源线通过电线和第一接合焊盘接收电力电压时，电压转换器电路被去激活。

8. 发明授权

US07983098B2 Adaptive regulator for idle state in a charge pump circuit of a memory device 有权
标题翻译：用于存储器件的电荷泵电路中的空闲状态的自适应调节器
公开(公告)号：US07983098B2
公开(公告)日：2011-07-19
申请号：US12571085
申请日：2009-09-30
申请人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
发明人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/145
摘要： An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
摘要翻译：公开了一种改善电子设备性能的装置和方法。当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

9. 发明申请

US20100074030A1 ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE 有权
标题翻译：用于存储器装置的充电泵电路中的空闲状态的自适应调节器
公开(公告)号：US20100074030A1
公开(公告)日：2010-03-25
申请号：US12571085
申请日：2009-09-30
申请人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
发明人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/02 , G11C5/145
摘要： An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
摘要翻译：公开了一种改善电子设备性能的装置和方法。当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

10. 发明授权

US07599231B2 Adaptive regulator for idle state in a charge pump circuit of a memory device 有权
标题翻译：用于存储器件的电荷泵电路中的空闲状态的自适应调节器
公开(公告)号：US07599231B2
公开(公告)日：2009-10-06
申请号：US11548319
申请日：2006-10-11
申请人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
发明人： Marco Passerini , Stefano Sivero , Andrea Sacco , Monica Marziani
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/145
摘要： An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
摘要翻译：公开了一种改善电子设备性能的装置和方法。当从电路中的线路或节点提供或去除高电压信号时，自适应电压发生器引入空闲电压状态。空闲状态减少了由于线路或节点中突然的电压变化引起的开关扰动的不良影响。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式