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1. 发明授权

US07525856B2 Apparatus and method to manage external voltage for semiconductor memory testing with serial interface 有权
标题翻译：使用串行接口管理半导体存储器测试的外部电压的装置和方法
公开(公告)号：US07525856B2
公开(公告)日：2009-04-28
申请号：US11696521
申请日：2007-04-04
申请人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
发明人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
IPC分类号： G11C29/00
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
摘要翻译：串行接口闪存设备包括数据/地址I / O引脚和时钟输入引脚。双向缓冲器耦合到数据/地址I / O引脚。包括数据方向控制的串行接口逻辑块耦合到时钟引脚，双向缓冲器，内部控制逻辑以及读取电压和修改电压发生器。第一开关耦合到读电压发生器和时钟缓冲器，第二开关耦合到修改电压发生器和时钟缓冲器，第一和第二开关各自具有控制输入。存储器驱动器通过第一和第二开关耦合到读取电压发生器和修改电压发生器。第一和第二寄存器耦合在串行接口逻辑与第一和第二开关之间。存储器阵列耦合到存储器驱动器和读取放大器，并且程序缓冲器耦合在串行接口逻辑和存储器驱动器之间。

2. 发明申请

US20080246504A1 APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR MEMORY TESTING WITH SERIAL INTERFACE 有权
标题翻译：用于串行接口的半导体存储器测试管理外部电压的装置和方法
公开(公告)号：US20080246504A1
公开(公告)日：2008-10-09
申请号：US11696521
申请日：2007-04-04
申请人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
发明人： Stefano Surico , Marco Passerini , Massimiliano Frulio , Alex Pojer
IPC分类号： G01R31/00
CPC分类号： G11C29/32 , G11C29/003 , G11C29/1201
摘要： A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.
摘要翻译：串行接口闪存设备包括数据/地址I / O引脚和时钟输入引脚。双向缓冲器耦合到数据/地址I / O引脚。包括数据方向控制的串行接口逻辑块耦合到时钟引脚，双向缓冲器，内部控制逻辑以及读取电压和修改电压发生器。第一开关耦合到读电压发生器和时钟缓冲器，第二开关耦合到修改电压发生器和时钟缓冲器，第一和第二开关各自具有控制输入。存储器驱动器通过第一和第二开关耦合到读取电压发生器和修改电压发生器。第一和第二寄存器耦合在串行接口逻辑与第一和第二开关之间。存储器阵列耦合到存储器驱动器和读取放大器，并且程序缓冲器耦合在串行接口逻辑和存储器驱动器之间。

3. 发明授权

US07920436B2 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US07920436B2
公开(公告)日：2011-04-05
申请号：US12336965
申请日：2008-12-17
申请人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
发明人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
IPC分类号： G11C7/00
CPC分类号： G11C7/062
摘要： A sense amplifier includes a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.
摘要翻译：读出放大器包括第一共源共栅晶体管，第二共源共栅晶体管，第一反馈电路，第二反馈电路和比较器。第一共源共栅晶体管的漏极直接连接到第一电压源。第一共源共栅晶体管的栅极连接到第一反馈电路和比较器的第一输入端，并且第一共源共栅晶体管的源极连接到第一反馈电路和第一列解码器。第二共源共栅晶体管的漏极直接连接到第二电压源。第二共源共栅晶体管的栅极连接到第二反馈电路和比较器的第二输入端，第二共源共栅晶体管的源极连接到第二反馈电路和第二列解码器。

4. 发明授权

US06339315B1 Measuring counter of the state of charge of the powering battery of an electronic appliance 有权
标题翻译：电子设备供电电池的充电状态的计数器
公开(公告)号：US06339315B1
公开(公告)日：2002-01-15
申请号：US09503652
申请日：2000-02-14
申请人： Claudia Castelli , Fabrizio Fraternali , Adalberto Mariani , Alex Pojer
发明人： Claudia Castelli , Fabrizio Fraternali , Adalberto Mariani , Alex Pojer
IPC分类号： H02J700
CPC分类号： G01R31/3606 , G01R31/3648
摘要： A charge counter for monitoring the charge of the battery state of an electronic device includes a sensing circuit of the charge and discharge current of the battery. The sensing circuit includes a differential amplifier having inputs coupled to the terminals of a sensing resistor of the battery current, a resettable integrator of the output signal of the amplifier, a first comparator and a second comparator of the output signal of the integrator generating a logic charge interrupt signal and a logic discharge interrupt signal, respectively. The sensing circuit also includes a switch for discharging the capacitance of the integrator momentarily closed by a logic circuit at every transition of the output signal of one or the other of the first and second comparators. Further, the sensing circuit includes a processor for the interrupts which monitors the state of charge of the battery, a timer for measuring the time elapsing from the start of a new integration ramp and the switching instant of either one of the first and second comparators, and a nonvolatile memory register containing the measure of the time interval of integration of the offset of the differential amplifier up to the switching of either of the first and second comparators.
摘要翻译：用于监视电子设备的电池状态的充电的计费计数器包括电池的充放电电流的感测电路。感测电路包括具有耦合到电池电流的感测电阻器的端子的输入的差分放大器，放大器的输出信号的可复位积分器，积分器的输出信号的第一比较器和第二比较器，其产生逻辑充电中断信号和逻辑放电中断信号。感测电路还包括用于在第一和第二比较器中的一个或另一个的输出信号的每个转变处，由逻辑电路暂时闭合的积分器的电容放电的开关。此外，感测电路包括用于监视电池的充电状态的中断的处理器，用于测量从新的积分斜坡开始经过的时间的定时器和第一和第二比较器中的任一个的切换时刻，以及非易失性存储寄存器，其包含将差分放大器的偏移积分到第一和第二比较器之一的切换的时间间隔的测量值。

5. 发明申请

US20100149896A1 SENSE AMPLIFIER 有权
标题翻译：感应放大器
公开(公告)号：US20100149896A1
公开(公告)日：2010-06-17
申请号：US12336965
申请日：2008-12-17
申请人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
发明人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
IPC分类号： G11C7/06 , H03K5/24
CPC分类号： G11C7/062
摘要： A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.
摘要翻译：读出放大器包括第一共源共栅晶体管，第二共源共栅晶体管，第一反馈电路，第二反馈电路和比较器。第一共源共栅晶体管的漏极直接连接到第一电压源。第一共源共栅晶体管的栅极连接到第一反馈电路和比较器的第一输入端，并且第一共源共栅晶体管的源极连接到第一反馈电路和第一列解码器。第二共源共栅晶体管的漏极直接连接到第二电压源。第二共源共栅晶体管的栅极连接到第二反馈电路和比较器的第二输入端，第二共源共栅晶体管的源极连接到第二反馈电路和第二列解码器。

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