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1. 发明授权

US07414891B2 Erase verify method for NAND-type flash memories 有权
标题翻译：擦除NAND型闪存的验证方法
公开(公告)号：US07414891B2
公开(公告)日：2008-08-19
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/00
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

2. 发明授权

US07333389B2 Column decoding architecture for flash memories 有权
标题翻译：闪存的列解码架构
公开(公告)号：US07333389B2
公开(公告)日：2008-02-19
申请号：US11126441
申请日：2005-05-11
申请人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
发明人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/26
摘要： An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
摘要翻译：用于闪存器件的列解码的改进方法和装置利用长度大于逻辑页长度的突发页。当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。只有当读取跨越突发页面边界时，存储器件才进入等待状态。这使存储器件进入等待状态的时间量最小化。在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。不需要对架构或列解码器选择器的数量进行更改。因此，同步读取期间的存储器访问时间得到改善。

3. 发明申请

US20060077746A1 Column decoding architecture for flash memories 有权
标题翻译：闪存的列解码架构
公开(公告)号：US20060077746A1
公开(公告)日：2006-04-13
申请号：US11126441
申请日：2005-05-11
申请人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Reggiori
发明人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Reggiori
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/26
摘要： An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
摘要翻译：用于闪存器件的列解码的改进方法和装置利用长度大于逻辑页长度的突发页。当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。只有当读取跨越突发页面边界时，存储器件才进入等待状态。这使存储器件进入等待状态的时间量最小化。在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。不需要对架构或列解码器选择器的数量进行更改。因此，同步读取期间的存储器访问时间得到改善。

4. 发明申请

US20080165585A1 ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES 有权
标题翻译：用于NAND型闪存存储器的擦除验证方法
公开(公告)号：US20080165585A1
公开(公告)日：2008-07-10
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

5. 发明申请

US20130193590A1 SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：包括电压转换器电路的半导体器件及制造半导体器件的方法
公开(公告)号：US20130193590A1
公开(公告)日：2013-08-01
申请号：US13363242
申请日：2012-01-31
申请人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
发明人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
IPC分类号： H01L23/49 , H01L21/50
CPC分类号： H01L23/50 , G11C5/147 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48669 , H01L2224/49113 , H01L2224/73265 , H01L2224/85205 , H03K17/223 , H03K19/0013 , H01L2924/00014 , H01L2924/20752 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.
摘要翻译：半导体器件包括第一接合焊盘，第二接合焊盘，接合到第一和第二接合焊盘中的所选择的接合焊盘的引线，电连接到第一接合焊盘的电源线，以及耦合到第二接合焊盘的电压转换器电路当焊丝接合到第二焊盘上时，电压转换器电路被激活以产生与电压转换器电路通过电线和第二接合焊盘接收的电压不同的内部电源电压，并且提供内部当电线连接到第一接合焊盘以允许电源线通过电线和第一接合焊盘接收电力电压时，电压转换器电路被去激活。

6. 发明授权

US07769943B2 Flexible, low cost apparatus and method to introduce and check algorithm modifications in a non-volatile memory 有权
标题翻译：灵活，低成本的装置和方法来引入和检查非易失性存储器中的算法修改
公开(公告)号：US07769943B2
公开(公告)日：2010-08-03
申请号：US11696288
申请日：2007-04-04
申请人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
发明人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
摘要翻译：闪速存储器包括输入/输出缓冲器，具有耦合到输入/输出缓冲器的存储器单元的存储器阵列以及行和列解码器，以及耦合到行和列解码器的电压发生器电路。微控制器耦合到命令用户界面。开关指令电路在命令用户界面的控制下，从只读存储器和从芯片到板上t锁存器选择性地向微控制器提供指令，耦合到输入/输出缓冲器。

7. 发明申请

US20080250191A1 FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY 有权
标题翻译：灵活，低成本的设备和方法来引导和检查非易失性存储器中的算法修改
公开(公告)号：US20080250191A1
公开(公告)日：2008-10-09
申请号：US11696288
申请日：2007-04-04
申请人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
发明人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
摘要翻译：闪速存储器包括输入/输出缓冲器，具有耦合到输入/输出缓冲器的存储器单元的存储器阵列以及行和列解码器，以及耦合到行和列解码器的电压发生器电路。微控制器耦合到命令用户界面。开关指令电路在命令用户界面的控制下，从只读存储器和从芯片到板上t锁存器选择性地向微控制器提供指令，耦合到输入/输出缓冲器。

8. 发明申请

US20060077714A1 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US20060077714A1
公开(公告)日：2006-04-13
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

9. 发明授权

US5822247A Device for generating and regulating a gate voltage in a non-volatile memory 失效
标题翻译：用于产生和调节非易失性存储器中的栅极电压的装置
公开(公告)号：US5822247A
公开(公告)日：1998-10-13
申请号：US775111
申请日：1996-12-30
申请人： Fabio Tassan Caser , Corrado Villa , Simone Bartoli
发明人： Fabio Tassan Caser , Corrado Villa , Simone Bartoli
IPC分类号： G11C5/14 , G11C8/08 , G11C16/16 , G11C16/30 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C5/147 , G11C8/08
摘要： The present invention relates to a device for generating and regulating a gate voltage in an electrically programmable non-volatile memory with single power supply of the type comprising a voltage booster driven by a clock signal applied to a first input terminal thereof and having an output terminal on which is produced a signal with higher voltage. This device comprises a lower regulator block and a programming switching block inserted in parallel each other between said output terminal of the voltage booster and an output terminal of the gate voltage generating and regulating device with said lower regulator block being driven by a plurality of switching signals to supply on the output terminal of the device a plurality of regulated voltages and feed the control gates of the non-volatile memory cells.
摘要翻译：本发明涉及一种用于在电可编程非易失性存储器中产生和调节栅极电压的装置，该单电源包括由施加到其第一输入端的时钟信号驱动的升压驱动器，并具有输出端在其上产生具有较高电压的信号。该装置包括在升压器的所述输出端子和栅极电压产生和调节装置的输出端子之间并联插入的下调节器块和编程切换块，所述下调节器块由多个开关信号驱动在装置的输出端子上提供多个调节电压并馈送非易失性存储单元的控制栅极。

10. 发明授权

US07345921B2 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US07345921B2
公开(公告)日：2008-03-18
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

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