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1. 发明申请

US20080136500A1 CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS 有权
标题翻译：用于产生多个输出电压的充电泵
公开(公告)号：US20080136500A1
公开(公告)日：2008-06-12
申请号：US11608941
申请日：2006-12-11
申请人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
发明人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

2. 发明授权

US07579902B2 Charge pump for generation of multiple output-voltage levels 有权
标题翻译：用于产生多个输出电压电平的电荷泵
公开(公告)号：US07579902B2
公开(公告)日：2009-08-25
申请号：US11608941
申请日：2006-12-11
申请人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
发明人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

3. 发明授权

US07430150B2 Method and system for providing sensing circuitry in a multi-bank memory device 有权
标题翻译：用于在多存储体存储器件中提供感测电路的方法和系统
公开(公告)号：US07430150B2
公开(公告)日：2008-09-30
申请号：US11123544
申请日：2005-05-05
申请人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
发明人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C11/34 , G11C16/06 , G11C7/00 , G11C7/02 , G11C7/06
CPC分类号： G11C8/12 , G11C5/025 , G11C7/06 , G11C16/26
摘要： A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.
摘要翻译：描述了一种用于提供多存储体存储器的方法和系统。该方法和系统包括提供多个银行。多个存储体中的每一个包括包括多个存储单元和模拟感测电路的至少一个阵列。该方法和系统还包括提供与多个存储体耦合的公共数字感测电路。

4. 发明申请

US20060083097A1 Method and system for providing sensing circuitry in a multi-bank memory device 有权
标题翻译：用于在多存储体存储器件中提供感测电路的方法和系统
公开(公告)号：US20060083097A1
公开(公告)日：2006-04-20
申请号：US11123544
申请日：2005-05-05
申请人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
发明人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C5/025 , G11C7/06 , G11C16/26
摘要： A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.
摘要翻译：描述了一种用于提供多存储体存储器的方法和系统。该方法和系统包括提供多个银行。多个存储体中的每一个包括包括多个存储单元和模拟感测电路的至少一个阵列。该方法和系统还包括提供与多个存储体耦合的公共数字感测电路。

5. 发明授权

US07414891B2 Erase verify method for NAND-type flash memories 有权
标题翻译：擦除NAND型闪存的验证方法
公开(公告)号：US07414891B2
公开(公告)日：2008-08-19
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Sivero , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/00
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

6. 发明授权

US07269058B2 System and method for preserving an error margin for a non-volatile memory 有权
标题翻译：用于保存非易失性存储器的错误余量的系统和方法
公开(公告)号：US07269058B2
公开(公告)日：2007-09-11
申请号：US11124939
申请日：2005-05-09
申请人： Massimiliano Frulio , Fabio Tassan Caser , Lorenzo Bedarida , Mirella Marsella
发明人： Massimiliano Frulio , Fabio Tassan Caser , Lorenzo Bedarida , Mirella Marsella
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C7/062 , G11C7/067 , G11C7/14 , G11C16/04 , G11C16/28 , G11C29/026 , G11C29/028 , G11C2207/063 , G11C2211/5645
摘要： A system and method for preserving an error margin for a non-volatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.
摘要翻译：一种用于保持非易失性存储器的误差容限的系统和方法，所述非易失性存储器包括存储器单元，耦合到被配置为镜像通过所述参考单元的电流的参考电流镜的参考单元。该系统包括耦合到存储器单元并被配置为镜像通过存储器单元的电流的存储器电流镜。读出放大器具有第一和第二输入。第一输入耦合到参考电流镜，第二输入耦合到存储器电流镜。读出放大器被配置为将存储器单元两端的电压与参考单元两端的电压进行比较。

7. 发明申请

US20060044885A1 System and method for preserving an error margin for a non-volatile memory 有权
标题翻译：用于保存非易失性存储器的错误余量的系统和方法
公开(公告)号：US20060044885A1
公开(公告)日：2006-03-02
申请号：US11124939
申请日：2005-05-09
申请人： Massimiliano Frulio , Fabio Tassan Caser , Lorenzo Bedarida , Mirella Marsella
发明人： Massimiliano Frulio , Fabio Tassan Caser , Lorenzo Bedarida , Mirella Marsella
IPC分类号： G11C5/14
CPC分类号： G11C29/50 , G11C7/062 , G11C7/067 , G11C7/14 , G11C16/04 , G11C16/28 , G11C29/026 , G11C29/028 , G11C2207/063 , G11C2211/5645
摘要： A system and method for preserving an error margin for a non-volatile memory that includes a memory cell, a reference cell coupled to a reference current mirror configured to mirror current through the reference cell. The system comprises a memory current mirror coupled to the memory cell and configured to mirror current through the memory cell. A sense amplifier has a first and a second input. The first input is coupled to the reference current mirror and the second input is coupled to the memory current mirror. The sense amplifier is configured to compare a voltage across the memory cell with a voltage across the reference cell.
摘要翻译：一种用于保持非易失性存储器的误差容限的系统和方法，所述非易失性存储器包括存储器单元，耦合到被配置为镜像通过所述参考单元的电流的参考电流镜的参考单元。该系统包括耦合到存储器单元并被配置为镜像通过存储器单元的电流的存储器电流镜。读出放大器具有第一和第二输入。第一输入耦合到参考电流镜，第二输入耦合到存储器电流镜。读出放大器被配置为将存储器单元两端的电压与参考单元两端的电压进行比较。

8. 发明授权

US07333389B2 Column decoding architecture for flash memories 有权
标题翻译：闪存的列解码架构
公开(公告)号：US07333389B2
公开(公告)日：2008-02-19
申请号：US11126441
申请日：2005-05-11
申请人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
发明人： Stefano Sivero , Simone Bartoli , Fabio Tassan Caser , Riccardo Riva Reggiori
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C16/26
摘要： An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
摘要翻译：用于闪存器件的列解码的改进方法和装置利用长度大于逻辑页长度的突发页。当发生初始地址的错位时，跨逻辑页面边界的有效读取是可能的。只有当读取跨越突发页面边界时，存储器件才进入等待状态。这使存储器件进入等待状态的时间量最小化。在优选实施例中，这通过对馈送三电平解码级列解码器的第三电平的控制信号的不同管理来实现。不需要对架构或列解码器选择器的数量进行更改。因此，同步读取期间的存储器访问时间得到改善。

9. 发明申请

US20080232169A1 NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES 审中-公开
标题翻译： NAND型存储器阵列采用高密度NOR形存储器件
公开(公告)号：US20080232169A1
公开(公告)日：2008-09-25
申请号：US11688740
申请日：2007-03-20
申请人： Massimiliano Frulio , Lorenzo Bedarida , Simone Bartoli , Fabio Tassan Caser
发明人： Massimiliano Frulio , Lorenzo Bedarida , Simone Bartoli , Fabio Tassan Caser
IPC分类号： G11C11/34
CPC分类号： G11C16/08 , G11C5/025 , G11C5/063
摘要： A flash memory integrated circuit includes a plurality of flash memory arrays. A global word line driver is associated with each array, each global word line driver coupled to a plurality of select lines. A plurality of sense amplifiers are individually coupled to a plurality of bit lines. A plurality of sub arrays in each array each include a plurality of NAND flash memory cells coupled to local word lines and local bit lines. A local word line driver is associated with each sub-array and coupled to the plurality of select lines and configured to drive ones of the local word lines in its sub array associated with selected ones of the plurality of NAND flash memory cells in its sub-array. A local bit line driver is coupled between selected ones of the local bit lines in each sub array and selected ones of the plurality of bit lines.
摘要翻译：闪存集成电路包括多个闪存阵列。全局字线驱动器与每个阵列相关联，每个全局字线驱动器耦合到多个选择线。多个读出放大器分别耦合到多个位线。每个阵列中的多个子阵列每个包括耦合到本地字线和局部位线的多个NAND快闪存储器单元。本地字线驱动器与每个子阵列相关联并且耦合到多个选择线，并且被配置为驱动其子阵列中的与本发明的子阵列中的多个NAND快闪存储器单元中的选定的一个相关联的本地字线中的一个，数组。局部位线驱动器耦合在每个子阵列中的局部位线中的选定的位线和多个位线中的选定的位线之间。

10. 发明授权

US06831499B2 Negative charge pump with bulk biasing 有权
标题翻译：带负电荷的负电荷泵
公开(公告)号：US06831499B2
公开(公告)日：2004-12-14
申请号：US10407615
申请日：2003-04-03
申请人： Giorgio Oddone , Massimiliano Frulio , Luca Figini , Fabio Tassan Caser
发明人： Giorgio Oddone , Massimiliano Frulio , Luca Figini , Fabio Tassan Caser
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/078
摘要： An n-channel MOS transistor negative-voltage charge pump is disclosed in which the bulks of the n-channel MOS transistors are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.
摘要翻译：公开了一种n沟道MOS晶体管负电压电荷泵，其中n沟道MOS晶体管的体积以这样的方式被偏置，以防止接通电荷泵结构的CMOS环境中固有的寄生双极晶体管。

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