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1. 发明授权

US06584530B2 Information processing system, bus arbiter, and bus controlling method 有权
标题翻译：信息处理系统，总线仲裁器和总线控制方法
公开(公告)号：US06584530B2
公开(公告)日：2003-06-24
申请号：US10173819
申请日：2002-06-19
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F1338
CPC分类号： G06F13/364
摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request, the bus arbiter refers to the access destination information and the data storage status of the storage and decides whether to give a bus occupation right to the bus master.
摘要翻译：本发明提供了一种用于防止执行诸如主存储器访问的事务的方法，以便通过具有低速IO访问的总线竞争阻塞，并且提高总线占用效率。用于防止执行诸如存储访问以避免总线阻塞的事务的装置竞争与低速IO访问。本发明包括第一总线，第二总线，连接到两个总线的多个模块，用于在两个总线之间执行信息协议转换的总线转换单元，用于仲裁总线主机的总线占用权请求的总线仲裁器和存储器，用于当访问目的地是预定模块时存储高达预定量的访问数据。每个总线主机输出接入目的地信息，当总线仲裁器判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存储的访问目的地信息和数据存储状态，并决定是否给出总线占领权掌握公交车主。

2. 发明授权

US06425037B1 Information processing system, bus arbiter, and bus controlling method 有权
标题翻译：信息处理系统，总线仲裁器和总线控制方法
公开(公告)号：US06425037B1
公开(公告)日：2002-07-23
申请号：US09407064
申请日：1999-09-28
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.
摘要翻译：本发明提供了一种用于防止诸如通过具有低速IO接入的总线竞争阻塞的主存储访问的事务的执行并提高总线占用效率的手段。本发明包括第一总线，第二总线，多个连接到两个总线的模块，用于在两个总线之间执行信息的协议转换的总线转换装置，用于仲裁总线主机的总线占用权请求的总线仲裁器，以及用于当存储访问数据达到预定量时存储访问数据的存储装置访问目的地是预定模块。每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存取装置的访问目的地信息和数据存储状态并决定是否给予巴士总线职业权。

3. 发明授权

US4812975A Emulation method 失效
标题翻译：仿真方法
公开(公告)号：US4812975A
公开(公告)日：1989-03-14
申请号：US629808
申请日：1984-07-11
申请人： Shigemi Adachi , Yoshitake Nakaosa , Yoshiki Fujioka
发明人： Shigemi Adachi , Yoshitake Nakaosa , Yoshiki Fujioka
IPC分类号： G06F9/48 , G06F5/00 , G06F9/455 , G06F15/00 , G06F9/44
CPC分类号： G06F9/45537 , G06F9/45554
摘要： A method for emulating programs in a system includes a plurality of first and second data processors having different instruction word sets. An instruction which interrupts the operating system on the first data processor is defined. When the instruction is detected in a program running on the first data processor, it is determined whether or not the instruction is an instruction associated with an input/output macro instruction. If it is found, as a result of the determination, that this is the case, an interrupt is caused in a program running on the second data processor which controls the emulation, and the input/output macro instruction output from an emulated program is translated into an input/output macro instuction for the operating system, thereby implementing an emulation with a minimized overhead.
摘要翻译：用于模拟系统中的程序的方法包括具有不同指令字集合的多个第一和第二数据处理器。定义了中断第一数据处理器上的操作系统的指令。当在第一数据处理器上运行的程序中检测到指令时，确定指令是否是与输入/输出宏指令相关联的指令。如果发现确定的结果是这种情况，则在控制仿真的第二数据处理器上运行的程序中引起中断，并且将来自仿真程序的输入/输出宏指令输出转换转化为操作系统的输入/输出宏指令，从而以最小化的开销来实现仿真。

4. 发明授权

US5821767A Information processing apparatus and backboard having on backboard side matching resistors suited to modules connected thereto 失效
标题翻译：信息处理装置和背板具有适于与其连接的模块的背板侧匹配电阻器
公开(公告)号：US5821767A
公开(公告)日：1998-10-13
申请号：US633309
申请日：1996-04-15
申请人： Hideki Osaka , Yukihiro Seki , Shigemi Adachi
发明人： Hideki Osaka , Yukihiro Seki , Shigemi Adachi
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , G11C11/401 , H03K19/00 , H04L25/02 , H03K17/16 , H03K19/0175
CPC分类号： H04L25/0278 , G06F13/4077 , H03K19/0005 , H04L25/028 , H04L25/0292
摘要： In an information processing apparatus including a backboard having a bus for transmitting signals therethrough, at least one module, and a connector to connect the bus to the module, the backboard includes two terminators disposed respectively at both ends of the bus for providing matched termination according to a characteristic impedance of the bus to which the module is connected and a matching resistor disposed between the bus and the module. The matching resistor has a resistance value Rm represented as Rm=Z1.multidot.k-Z0/2(0.8
摘要翻译：在包括具有用于发送信号的总线的背板的信息处理装置中，至少一个模块和用于将总线连接到模块的连接器，所述背板包括分别设置在总线两端的两个端子，用于根据连接到模块所连接的总线的特性阻抗和布置在总线和模块之间的匹配电阻。匹配电阻具有表示为Rm = Z1xk-Z0 / 2（0.8

5. 发明授权

US6021455A Method and system for arbitrating a bus according to the status of a buffer and destination information 失效
标题翻译：根据缓冲区和目的地信息的状态仲裁总线的方法和系统
公开(公告)号：US6021455A
公开(公告)日：2000-02-01
申请号：US708324
申请日：1996-09-05
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.
摘要翻译：一种信息处理系统，包括第一总线，第二总线，连接到两个总线的多个模块，用于仲裁总线主机的总线访问请求的总线仲裁器，以及用于存储高达预定量的访问数据的存储装置，当访问目的地信息指示所述模块是访问目的地时，模块之一。每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断总线主机之一发出总线访问请求时，总线仲裁器是指预定量的访问目的地信息是否完全存储在存储器中意味着，并决定是否给总线访问总线主控。

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