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1. 发明授权

US06425037B1 Information processing system, bus arbiter, and bus controlling method 有权
标题翻译：信息处理系统，总线仲裁器和总线控制方法
公开(公告)号：US06425037B1
公开(公告)日：2002-07-23
申请号：US09407064
申请日：1999-09-28
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.
摘要翻译：本发明提供了一种用于防止诸如通过具有低速IO接入的总线竞争阻塞的主存储访问的事务的执行并提高总线占用效率的手段。本发明包括第一总线，第二总线，多个连接到两个总线的模块，用于在两个总线之间执行信息的协议转换的总线转换装置，用于仲裁总线主机的总线占用权请求的总线仲裁器，以及用于当存储访问数据达到预定量时存储访问数据的存储装置访问目的地是预定模块。每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存取装置的访问目的地信息和数据存储状态并决定是否给予巴士总线职业权。

2. 发明授权

US6021455A Method and system for arbitrating a bus according to the status of a buffer and destination information 失效
标题翻译：根据缓冲区和目的地信息的状态仲裁总线的方法和系统
公开(公告)号：US6021455A
公开(公告)日：2000-02-01
申请号：US708324
申请日：1996-09-05
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.
摘要翻译：一种信息处理系统，包括第一总线，第二总线，连接到两个总线的多个模块，用于仲裁总线主机的总线访问请求的总线仲裁器，以及用于存储高达预定量的访问数据的存储装置，当访问目的地信息指示所述模块是访问目的地时，模块之一。每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断总线主机之一发出总线访问请求时，总线仲裁器是指预定量的访问目的地信息是否完全存储在存储器中意味着，并决定是否给总线访问总线主控。

3. 发明授权

US06584530B2 Information processing system, bus arbiter, and bus controlling method 有权
标题翻译：信息处理系统，总线仲裁器和总线控制方法
公开(公告)号：US06584530B2
公开(公告)日：2003-06-24
申请号：US10173819
申请日：2002-06-19
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F1338
CPC分类号： G06F13/364
摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request, the bus arbiter refers to the access destination information and the data storage status of the storage and decides whether to give a bus occupation right to the bus master.
摘要翻译：本发明提供了一种用于防止执行诸如主存储器访问的事务的方法，以便通过具有低速IO访问的总线竞争阻塞，并且提高总线占用效率。用于防止执行诸如存储访问以避免总线阻塞的事务的装置竞争与低速IO访问。本发明包括第一总线，第二总线，连接到两个总线的多个模块，用于在两个总线之间执行信息协议转换的总线转换单元，用于仲裁总线主机的总线占用权请求的总线仲裁器和存储器，用于当访问目的地是预定模块时存储高达预定量的访问数据。每个总线主机输出接入目的地信息，当总线仲裁器判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存储的访问目的地信息和数据存储状态，并决定是否给出总线占领权掌握公交车主。

4. 发明授权

US06748463B1 Information processor with snoop suppressing function, memory controller, and direct memory access processing method 失效
标题翻译：具有窥探抑制功能的信息处理器，存储器控制器和直接存储器存取处理方法
公开(公告)号：US06748463B1
公开(公告)日：2004-06-08
申请号：US09463599
申请日：2000-06-22
申请人： Masahide Tsuboi , Takashi Moriyama , Hiroshi Murashima , Masumi Terao , Michinori Naitoh , Koichi Okazawa , Masaya Umemura
发明人： Masahide Tsuboi , Takashi Moriyama , Hiroshi Murashima , Masumi Terao , Michinori Naitoh , Koichi Okazawa , Masaya Umemura
IPC分类号： G06F1314
CPC分类号： G06F12/0835
摘要： An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In response to a DMA request from the I/O device, a memory controller connected to both buses and to a main memory compares previous snoop addresses stored in a buffer memory of the memory controller with a current address contained in the DMA request to check whether the current DMA request is coincident with the past snoop process. If the comparison indicates a coincident snoop process, a snoop access process request is inhibited to be output to the system bus and cache memory. With this operation, the number of snoop accesses for DMAs to the same block of the cache memory can be reduced and a time during which the system bus is occupied can be shortened, to thereby improve the system performance.
摘要翻译：具有分级总线结构的信息处理设备，其具有连接到中央处理单元和高速缓冲存储器的系统总线以及连接到I / O设备的I / O总线。响应于来自I / O设备的DMA请求，连接到总线和主存储器的存储器控制器将存储在存储器控制器的缓冲存储器中的先前侦听地址与包含在DMA请求中的当前地址进行比较，以检查是否当前的DMA请求与过去的窥探过程一致。如果比较指示一致的窥探过程，则禁止窥探访问过程请求输出到系统总线和高速缓冲存储器。通过该操作，可以减少DMA到高速缓冲存储器的同一块的窥探访问次数，并且可以缩短系统总线占用的时间，从而提高系统性能。

5. 发明授权

US07584431B2 Communication system and terminal units connected thereto 有权
标题翻译：通信系统和与其连接的终端单元
公开(公告)号：US07584431B2
公开(公告)日：2009-09-01
申请号：US10724778
申请日：2003-12-02
申请人： Hiroi Kazushige , Nobukazu Kondo , Tsutomu Hara , Tooru Yokozawa , Kazuchika Ogiwara , Masaya Umemura , Shinichiro Okamura
发明人： Hiroi Kazushige , Nobukazu Kondo , Tsutomu Hara , Tooru Yokozawa , Kazuchika Ogiwara , Masaya Umemura , Shinichiro Okamura
IPC分类号： G06F3/00
CPC分类号： H04L29/06 , H04L67/38
摘要： A communication system including a network and at least two terminal units connected thereto. Each terminal unit includes a session controlling unit for controlling a session for enabling transmission/receiving of voice, image, handwritten data to/from the remote terminal unit individually, and a display unit for displaying the image and the handwritten data. The image data and the handwritten data are overlapped and displayed on a display of the display unit.
摘要翻译：一种通信系统，包括网络和与其连接的至少两个终端单元。每个终端单元包括会话控制单元，用于控制会话以使得能够单独地向/从远程终端单元发送/接收语音，图像，手写数据，以及用于显示图像和手写数据的显示单元。图像数据和手写数据被重叠并显示在显示单元的显示器上。

6. 发明申请

US20070197182A1 Radio equipment 失效
公开(公告)号：US20070197182A1
公开(公告)日：2007-08-23
申请号：US11785127
申请日：2007-04-16
申请人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
发明人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
IPC分类号： H04B1/06
CPC分类号： H04B1/40 , H04B1/109 , H04B1/52
摘要： A radio equipment, wherein an attenuator (10) is inserted between antennas (91, 92) and a radio module (2), and output and input sensitivities are raised and lowered simultaneously so as to keep the balance of a radio covering range with an input receiver coverage at a constant, and the antenna (91) and the antenna (92) with attenuator are switched over by a switch (8) to increase and decrease the radio coverage range and input receiver coverage while keeping the balance of the dynamic radio coverage range with the input receiver coverage.

7. 发明申请

US20050101360A1 Radio equipment 失效
标题翻译：无线电设备
公开(公告)号：US20050101360A1
公开(公告)日：2005-05-12
申请号：US10399679
申请日：2001-10-19
申请人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
发明人： Masaya Umemura , Yukihide Inagaki , Isao Takita , Tsutomu Hara
IPC分类号： H04B1/10 , H04B1/38 , H04B1/3822 , H04B1/44 , H03C7/02 , H04B1/02 , H04B7/02
CPC分类号： H04B1/40 , H04B1/109 , H04B1/52
摘要： A radio equipment, wherein an attenuator (10) is inserted between antennas (91, 92) and a radio module (2), and output and input sensitivities are raised and lowered simultaneously so as to keep the balance of a radio covering range with an input receiver coverage at a constant, and the antenna (91) and the antenna (92) with attenuator are switched over by a switch (8) to increase and decrease the radio coverage range and input receiver coverage while keeping the balance of the dynamic radio coverage range with the input receiver coverage.
摘要翻译：一种无线电设备，其中在天线（91,92）和无线电模块（2）之间插入衰减器（10），并且输出和输入灵敏度被同时升高和降低，以便将无线电覆盖范围的平衡保持为以恒定的输入接收机覆盖，并且具有衰减器的天线（91）和天线（92）由开关（8）切换，以增加和减少无线电覆盖范围并输入接收机覆盖，同时保持动态无线电的平衡覆盖范围与输入接收机覆盖范围。

8. 发明申请

US20050031092A1 Telephone communication system 失效
标题翻译：电话通讯系统
公开(公告)号：US20050031092A1
公开(公告)日：2005-02-10
申请号：US10651258
申请日：2003-08-29
申请人： Masaya Umemura , Takeo Tomokane , Kazushige Hiroi
发明人： Masaya Umemura , Takeo Tomokane , Kazushige Hiroi
IPC分类号： H04B7/24 , H04M11/00 , H04N7/14 , H04Q7/38
CPC分类号： H04N7/147 , H04M3/42263 , H04M3/58 , H04M2201/20 , H04M2203/2094 , H04N7/142
摘要： A video-phone call with a portable video-phone terminal is enabled for a cellular phone which has not video-phone service provided, by making use of cameras and display devices placed on the street. For a video-phone call to a portable video-phone terminal, a media converter in a service center distributes data so as to send video data to a public communication terminal on the street, and voice data to a cellular phone without video recording/reproducing capability. A call agent in a service center issues an ID in response to a request from the cellular phone without video recording/reproducing capability on voice call. This ID may be received by a service center via a detector such as a sensor deployed on the street, to provide a video-phone service by using a public communication terminal on the street in the vicinity of the detector.
摘要翻译：通过使用放置在街道上的相机和显示设备，可以为没有提供视频电话服务的蜂窝电话启用具有便携式视频电话终端的视频电话。对于对便携式视频电话终端的视频电话呼叫，服务中心的媒体转换器分配数据，以将视频数据发送到街道上的公共通信终端，并将语音数据发送到蜂窝电话而不进行视频记录/再现能力。响应于来自蜂窝电话的请求而在语音呼叫中没有视频记录/再现能力的情况下，服务中心的呼叫代理发出ID。该ID可以由服务中心经由诸如部署在街道上的传感器的检测器接收，以通过使用在检测器附近的街道上的公共通信终端来提供视频电话服务。

9. 发明授权

US5933623A Synchronous data transfer system 失效
标题翻译：同步数据传输系统
公开(公告)号：US5933623A
公开(公告)日：1999-08-03
申请号：US736212
申请日：1996-10-25
申请人： Masaya Umemura , Toshitsugu Takekuma
发明人： Masaya Umemura , Toshitsugu Takekuma
IPC分类号： G06F13/42 , G06F15/163
CPC分类号： G06F13/4243
摘要： A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit. Each node includes at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit in response to the phase reference signal, and a transfer end signal indicating an end of transferring the data, respectively, in synchronism with the clock signal. A phase reference signal bus is connected to each node. A data bus is connected to each node for transmitting the data and a transfer end signal bus is connected to each node for transmitting the transfer end signal. A sender node includes a sending unit for sending data to a receiver node with a delay after the phase reference signal transmitted to the phase reference signal bus by the sender node, and sending simultaneously the transfer end signal to the receiver node. The receiver node includes a selecting unit for converting the phase reference signal into phase information to select a clock signal having a predetermined phase based on the received clock signal and a receiving unit for receiving data from the sender node using the selected clock signal.
摘要翻译：同步数据传输系统包括振荡电路和连接到振荡电路的多个节点。每个节点至少包括一个内部逻辑电路。每个节点输出指示时钟信号的相位的相位参考信号，响应于相位参考信号由内部逻辑电路处理的数据，以及指示分别传送数据的结束的传送结束信号，与时钟信号。相位参考信号总线连接到每个节点。数据总线连接到每个节点用于发送数据，并且传送结束信号总线连接到每个节点用于发送传送结束信号。发送方节点包括发送单元，用于在发送方节点将相位参考信号发送到相位参考信号总线之后延迟地向接收方节点发送数据，同时将发送结束信号发送到接收方节点。接收器节点包括：选择单元，用于将相位参考信号转换成相位信息，以基于接收到的时钟信号选择具有预定相位的时钟信号;以及接收单元，用于使用所选择的时钟信号从发送器节点接收数据。

10. 发明申请

US20090222798A1 Information Processing Apparatus 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20090222798A1
公开(公告)日：2009-09-03
申请号：US12332397
申请日：2008-12-11
申请人： Shinya IGUCHI , Takatoshi Kato , Masaya Umemura , Nobuaki Kohinata , Yasushi Nagai , Hiroshi Nakagoe , Keitaro Okasaki , Hirotaka Moribe , Takeshi Asahi
发明人： Shinya IGUCHI , Takatoshi Kato , Masaya Umemura , Nobuaki Kohinata , Yasushi Nagai , Hiroshi Nakagoe , Keitaro Okasaki , Hirotaka Moribe , Takeshi Asahi
IPC分类号： G06F9/45
CPC分类号： G06F8/52
摘要： A mobile device includes a memory for storing therein a subroutine management table to manage kinds of existing codes out of native code, first code and second code for a plurality of subroutines contained in content, a virtual machine, a precompile circuit for producing second code from first code and a subroutine management circuit for changing over processing in accordance with the kind of existing code for subroutine called up during execution of content. The subroutine management circuit judges kind of existing code with reference to the subroutine management table when the processing is changed over.
摘要翻译：移动设备包括一个存储器，用于在其中存储子程序管理表以管理内容中的现有代码的种类，用于内容中包含的多个子程序的第一代码和第二代码，虚拟机，用于从第第一代码和子程序管理电路，用于根据在执行内容期间调用的子程序的现有代码的种类来改变处理。当处理转换时，子程序管理电路参考子程序管理表来判断现有代码的种类。

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