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1. 发明授权

US08536017B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08536017B2
公开(公告)日：2013-09-17
申请号：US13363312
申请日：2012-01-31
申请人： Masaru Kadoshima , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Masaru Kadoshima , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
摘要翻译：在半导体衬底的主表面上形成聚硅氮烷膜，使得埋在宽度为0.2μm或更小的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平，埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

2. 发明申请

US20120208346A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120208346A1
公开(公告)日：2012-08-16
申请号：US13363312
申请日：2012-01-31
申请人： Masaru KADOSHIMA , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Masaru KADOSHIMA , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
摘要翻译：在半导体衬底的主表面上形成聚硅氮烷膜，使得掩埋在宽度为0.2μm以下的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平，埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

3. 发明申请

US20100283108A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100283108A1
公开(公告)日：2010-11-11
申请号：US12765571
申请日：2010-04-22
申请人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L27/088 , H01L29/06 , H01L21/762
CPC分类号： H01L29/0653 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02337 , H01L21/3105 , H01L21/76205 , H01L21/76229 , H01L27/088
摘要： To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
摘要翻译：提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

4. 发明授权

US08384187B2 Semiconductor device with shallow trench isolation 有权
标题翻译：具有浅沟槽隔离的半导体器件
公开(公告)号：US08384187B2
公开(公告)日：2013-02-26
申请号：US12765571
申请日：2010-04-22
申请人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/762
CPC分类号： H01L29/0653 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02337 , H01L21/3105 , H01L21/76205 , H01L21/76229 , H01L27/088
摘要： To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
摘要翻译：提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

5. 发明授权

US08587085B2 Semiconductor device with trench isolation having a diffusion preventing film and manufacturing method thereof 有权
标题翻译：具有沟槽隔离的半导体器件具有防扩散膜及其制造方法
公开(公告)号：US08587085B2
公开(公告)日：2013-11-19
申请号：US13286699
申请日：2011-11-01
申请人： Katsuyuki Horita
发明人： Katsuyuki Horita
IPC分类号： H01L21/76 , H01L21/70
CPC分类号： H01L21/76229 , H01L29/6659 , H01L29/7833
摘要： There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0≦x
摘要翻译：提供了一种能够在由沟槽型元件隔离部分包围的有源区域中形成的场效应晶体管中提供期望的操作特性的技术。元件隔离部分包括沟槽型元件隔离膜，各自包括硅膜或氧化硅膜的扩散防止膜，并且在沟槽型元件隔离膜的顶表面上形成厚度为10至20nm的氧化硅形成在扩散防止膜的上表面上的厚度为0.5〜2nm的膜。防扩散膜的组成为SiOx（0 @ x <2）。沟槽型元件隔离膜和氧化硅膜的组成均为SiO 2。

6. 发明授权

US08043918B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US08043918B2
公开(公告)日：2011-10-25
申请号：US12840430
申请日：2010-07-21
申请人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
发明人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
IPC分类号： H01L21/336
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.
摘要翻译：为了以高生产率制造能够通过沟槽型元件隔离可靠地实现元件隔离并且能够有效地防止相邻元件的电位影响其他节点的半导体器件，制造半导体器件的方法包括：形成第一层; 通过蚀刻第一层和衬底形成沟槽的步骤; 热氧化沟槽内壁的步骤; 在包括沟槽的衬底上沉积膜厚度等于或大于沟槽的沟槽宽度的一半的第一导电膜的步骤; 通过CMP方法从第一层除去第一导电膜并保持第一导电膜仅留在沟槽中的步骤; 在沟槽内各向异性蚀刻第一导电膜的步骤，以调节导电膜的高度，使其低于衬底表面的高度; 通过CVD法在第一导电膜上沉积绝缘膜以将第一导电膜的上部嵌入沟槽内的步骤; 通过CMP方法使绝缘膜平坦化的步骤; 以及去除第一层的步骤。

7. 发明授权

US07791163B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07791163B2
公开(公告)日：2010-09-07
申请号：US11577878
申请日：2005-10-18
申请人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
发明人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
IPC分类号： H01L29/768
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.
摘要翻译：在制造半导体器件的过程中，在衬底上形成第一层，并且蚀刻第一层和衬底以形成沟槽。沟槽的内壁被热氧化。在包括沟槽内部的衬底上沉积厚度等于或大于沟槽宽度的一半的第一导电膜。通过化学机械抛光去除第一层上的第一导电膜，使得第一导电膜仅保留在沟槽中。通过各向异性蚀刻第一导电膜，将沟槽中的第一导电膜的高度调节为低于衬底的表面。通过化学气相沉积在衬底上沉积绝缘膜以覆盖沟槽中的第一导电膜的上表面。绝缘膜通过化学机械抛光而变平，第一层被去除。

8. 发明申请

US20100190306A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM 审中-公开
标题翻译：制造半导体器件的方法，其能够抑制由形成绝缘膜形成的掺杂通道区域中的浓度浓度降低
公开(公告)号：US20100190306A1
公开(公告)日：2010-07-29
申请号：US12754097
申请日：2010-04-05
申请人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
发明人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
摘要翻译：提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。在形成氧化硅膜和氮化硅膜的情况下，在对角上方沿Y方向注入p型杂质离子。对于离子注入的注入角度α，采用满足关系tan-1（W2 / T）<α＆nlE; tan-1（W1 / T）的植入角度，其中W1是第一部分和第四部分和第三部分和第六部分之间的间隔; W2是第二部分和第五部分之间的间隔; T是氧化硅膜和氮化硅膜的总膜厚。当将注入角度α控制在该范围内时，杂质离子通过氧化硅膜注入第二侧表面和第五侧表面。

9. 发明授权

US06998319B2 Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film 失效
公开(公告)号：US06998319B2
公开(公告)日：2006-02-14
申请号：US10730099
申请日：2003-12-09
申请人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
发明人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1(W2/T)

10. 发明申请

US20060027883A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060027883A1
公开(公告)日：2006-02-09
申请号：US11241921
申请日：2005-10-04
申请人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
发明人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
IPC分类号： H01L29/94
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method. An MOSFET has a trench-type element isolation structure (2) formed in the main surface of a semiconductor substrate (1), a pair of extensions (3) and source/drain regions (4) selectively formed in the main surface of the semiconductor substrate (1) to face each other through a channel region (50), a silicon oxide film (5) formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) formed on sides of the silicon oxide film (5), a gate insulating film (7) formed on the main surface of the semiconductor substrate (1) in the part in which the channel region (50) is formed, and a gate electrode (8) formed to fill a recessed portion in an inversely tapered form formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译：本发明的目的是获得其中通道长度减小而不增加栅极电阻以实现更高的操作速度的半导体器件及其制造方法。 MOSFET具有形成在半导体衬底（1）的主表面中的沟槽型元件隔离结构（2），在半导体的主表面中选择性地形成的一对延伸部（3）和源极/漏极区域（4）衬底（1）通过沟道区域（50）彼此面对，通过硅氧化膜形成在沟槽型元件隔离结构（2）上和源极/漏极区域（4）上的氧化硅膜（5）（12），形成在氧化硅膜（5）的侧面上的侧壁（6），形成在半导体衬底（1）的主表面上的沟道区域（50）的部分中的栅极绝缘膜（7）以及形成为以由侧壁（6）的侧面和栅极绝缘膜（7）的上表面形成的倒锥形状填充凹部的栅电极（8）。

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