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1. 发明授权

US08536017B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08536017B2
公开(公告)日：2013-09-17
申请号：US13363312
申请日：2012-01-31
申请人： Masaru Kadoshima , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Masaru Kadoshima , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
摘要翻译：在半导体衬底的主表面上形成聚硅氮烷膜，使得埋在宽度为0.2μm或更小的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平，埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

2. 发明申请

US20120208346A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120208346A1
公开(公告)日：2012-08-16
申请号：US13363312
申请日：2012-01-31
申请人： Masaru KADOSHIMA , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Masaru KADOSHIMA , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
摘要翻译：在半导体衬底的主表面上形成聚硅氮烷膜，使得掩埋在宽度为0.2μm以下的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平，埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

3. 发明申请

US20120045876A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120045876A1
公开(公告)日：2012-02-23
申请号：US13183996
申请日：2011-07-15
申请人： Takaaki KAWAHARA , Shinsuke Sakashita , Masaru Kadoshima , Hiroshi Umeda
发明人： Takaaki KAWAHARA , Shinsuke Sakashita , Masaru Kadoshima , Hiroshi Umeda
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate.
摘要翻译：提供了能够防止包括具有高介电常数栅极绝缘膜和金属栅电极的CMISFET的半导体器件中的n沟道型MISFET和p沟道型MISFET的阈值电压增加的技术。当为了调整CMISFET的阈值而将稀土元素或铝引入到作为高介电常数栅极绝缘膜的Hf的绝缘膜中时，包括几乎不含有氧的镧膜的阈值调整层和在nMIS形成区域和pMIS形成区域中分别在Hf的绝缘膜上形成包含几乎不含氧的铝膜的阈值调整层。这防止氧从阈值调节层扩散到含Hf的绝缘膜和半导体衬底的主表面。

4. 发明申请

US20110284971A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110284971A1
公开(公告)日：2011-11-24
申请号：US13109736
申请日：2011-05-17
申请人： Shinsuke SAKASHITA , Takaaki Kawahara , Masaru Kadoshima , Masao Inoue , Hiroshi Umeda
发明人： Shinsuke SAKASHITA , Takaaki Kawahara , Masaru Kadoshima , Masao Inoue , Hiroshi Umeda
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823857 , H01L21/28088 , H01L27/092 , H01L29/513 , H01L29/518 , H01L29/66492
摘要： There are provided a semiconductor device in which the threshold voltage of a p-channel field effect transistor is reliably controlled to allow a desired characteristic to be obtained, and a manufacturing method thereof. As a heat treatment performed at a temperature of about 700 to 900° C. proceeds, in an element formation region, aluminum (Al) in an aluminum (Al) film is diffused into a hafnium oxynitride (HfON) film, and thereby added as an element to the hafnium oxynitride (HfON) film. In addition, aluminum (Al) and titanium (Ti) in a hard mask formed of a titanium aluminum nitride (TiAlN) film are diffused into the hafnium oxynitride (HfON) film, and thereby added as elements to the hafnium oxynitride (HfON) film.
摘要翻译：提供一种可以可靠地控制p沟道场效应晶体管的阈值电压以获得期望特性的半导体器件及其制造方法。当在700〜900℃左右的温度下进行热处理时，在元素形成区域中，将铝（Al）膜中的铝（Al）扩散到氮氧化铪（HfON）膜中，铪氧氮化铪（HfON）膜的元素。另外，由氮化钛（TiAlN）膜形成的硬掩模中的铝（Al）和钛（Ti）扩散到氮氧化铪（HfON）膜中，从而作为元素添加到氮氧化铪（HfON）膜。

5. 发明授权

US06675866B2 System for monitoring molding machine and hydrostatic molding machine 有权
标题翻译：成型机和静液压成型机监控系统
公开(公告)号：US06675866B2
公开(公告)日：2004-01-13
申请号：US10009642
申请日：2001-12-12
申请人： Hironobu Amano , Yasuo Moribe , Hiroshi Umeda , Mitsuyuki Matsushita
发明人： Hironobu Amano , Yasuo Moribe , Hiroshi Umeda , Mitsuyuki Matsushita
IPC分类号： B22D1732
CPC分类号： B22C15/28 , B22C15/24 , B22C19/04
摘要： To provide a monitoring system for remotely monitoring the operation of a molding apparatus or an air-flow and press molding apparatus. The monitoring systems for monitoring a molding apparatus and an air-flow and press molding apparatus include sensors, a local unit, and a remote unit. The local unit transmits the signals associated with the required attributes, which are measured by the sensors, of the molding apparatus to the remote unit via the communication network. The remote unit is designed so that it receives the signals transmitted from the local unit; thereby the user can monitor the molding apparatus or the air-flow and press molding apparatus remotely at the production and operation by them.
摘要翻译：提供用于远程监视模制设备或气流和压制成型设备的操作的监控系统。用于监测成型设备和空气流动和压制成型设备的监控系统包括传感器，本地单元和远程单元。本地单元经由通信网络将与成型设备所测量的所需属性相关联的信号传送到远程单元。遥控单元被设计成接收从本地单元发送的信号; 从而用户可以在生产和操作时远程监控成型设备或气流和压模设备。

6. 发明授权

US06521509B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06521509B2
公开(公告)日：2003-02-18
申请号：US09887322
申请日：2001-06-25
申请人： Akinobu Teramoto , Kousuke Yagi , Hiroshi Umeda
发明人： Akinobu Teramoto , Kousuke Yagi , Hiroshi Umeda
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A highly reliable semiconductor device is provided. A silicon nitride film having an opening is formed on a main surface of a silicon substrate. The opening is formed with a side surface. The silicon substrate is etched using the silicon nitride film as a mask to form a trench. The side surface of the silicon nitride film is altered in quality to form a silicon oxide film. A silicon oxide film filling the trench is formed in contact with the silicon oxide film. The silicon nitride film is removed with the silicon oxide film in contact with the silicon oxide film remaining.

7. 发明授权

US06349127B1 Pulley and CT scanner 有权
标题翻译：皮带轮和CT扫描仪
公开(公告)号：US06349127B1
公开(公告)日：2002-02-19
申请号：US09157355
申请日：1998-09-19
申请人： Hiroshi Umeda
发明人： Hiroshi Umeda
IPC分类号： A61B603
CPC分类号： A61B6/035 , F16H55/42 , F16H55/46
摘要： With a view of facilitating the manufacture and reducing the cost, a pulley according to the present invention comprises an annular portion 100 formed by laminating rings 110, 120 and 130 and a tooth portion formed along a circumferential surface of the annular portion 100, the tooth portion comprising a plurality of resin teeth having blades formed on the side opposite to the side which is opposed to the circumferential surface of the annular portion. The rings 110, 120 and 130 are divided into a plurality of arcuate plates 111, 112, 113, 121, 122, 123, 131, 132 and 133.
摘要翻译：为了便于制造和降低成本，根据本发明的滑轮包括通过层叠环110,120和130而形成的环形部分100和沿着环形部分100的圆周表面形成的齿部分，齿部部分包括多个树脂齿，所述树脂齿具有形成在与所述环形部分的周向表面相对的一侧相反侧的叶片。环110,120和130被分成多个弧形板111,112,113,121,122,123,131,132和133。

8. 发明申请

US20050093428A1 Semiconductor light-emitting device 有权
标题翻译：半导体发光装置
公开(公告)号：US20050093428A1
公开(公告)日：2005-05-05
申请号：US10969015
申请日：2004-10-21
申请人： Kazuaki Kaneko , Hiroshi Umeda , Kazuaki Sasaki , Junichi Nakamura
发明人： Kazuaki Kaneko , Hiroshi Umeda , Kazuaki Sasaki , Junichi Nakamura
IPC分类号： H01L33/14 , H01L33/30 , H01L33/38 , H01L33/40 , H01L33/62 , H05B33/00 , H05B33/14
CPC分类号： H01L33/145 , H01L2224/48463 , H01L2924/3025 , H01L2924/00
摘要： A semiconductor light-emitting device includes: a semiconductor substrate; a light-emitting layer formed on the semiconductor substrate; a current-blocking layer formed on a part of the light-emitting layer for restricting light-emission; a current-spreading layer formed on the current-blocking layer and the other part of the light-emitting layer; a front electrode formed on the current-spreading layer; and a rear electrode formed on a rear side of the semiconductor substrate. The current-blocking layer is composed of a central region and an outer region which surrounds the central region via a part of the current-spreading layer, so that a light-emitting region that appears on a front surface of the device has an annular shape. The front electrode and the central region of the current-blocking layer are opposed to each other.
摘要翻译：半导体发光器件包括：半导体衬底; 形成在所述半导体基板上的发光层; 形成在用于限制发光的发光层的一部分上的电流阻挡层; 形成在电流阻挡层和发光层的另一部分上的电流扩散层; 形成在电流扩展层上的前电极; 以及形成在半导体基板的后侧的后电极。电流阻挡层由中心区域和外部区域构成，该区域通过电流扩展层的一部分围绕中心区域，使得出现在器件的前表面上的发光区域具有环形形状。电流阻挡层的前电极和中心区域彼此相对。

9. 发明授权

US06812536B2 MOSFET with graded gate oxide layer 失效
标题翻译：具有梯度栅氧化层的MOSFET
公开(公告)号：US06812536B2
公开(公告)日：2004-11-02
申请号：US10383753
申请日：2003-03-10
申请人： Shuichi Ueno , Yukio Nishida , Hiroshi Umeda , Kenichi Ohto , Takashi Terauchi , Shigeru Shiratake , Akinori Kinugasa
发明人： Shuichi Ueno , Yukio Nishida , Hiroshi Umeda , Kenichi Ohto , Takashi Terauchi , Shigeru Shiratake , Akinori Kinugasa
IPC分类号： H01L2976
CPC分类号： H01L29/42368 , H01L21/28247
摘要： A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.
摘要翻译：作为栅极氧化膜的微笑氧化膜形成在由掺杂多晶硅层，钨层和SiON层构成的三层多金属栅极的下方。微笑氧化膜具有位于多金属栅极的边缘下方的第一区域和位于多金属栅极的中心部分下方的第二区域。第一区域的膜厚度大于第二区域的膜厚度。与多晶硅层相比具有小的氧扩散速率的抗氧化膜完全覆盖多金属栅极而不暴露。

10. 发明授权

US5645502A Phased continuously variable transmission chain 失效
标题翻译：分阶段无级变速传动链
公开(公告)号：US5645502A
公开(公告)日：1997-07-08
申请号：US543441
申请日：1995-10-16
申请人： Shozo Wakabayashi , Yukio Tomimura , Koji Morishige , Hiroshi Umeda , Park Woo Serk , Mark Alan Boshart
发明人： Shozo Wakabayashi , Yukio Tomimura , Koji Morishige , Hiroshi Umeda , Park Woo Serk , Mark Alan Boshart
IPC分类号： F16G5/18 , F16H9/24 , F16H7/00
CPC分类号： F16H9/24 , F16G5/18
摘要： The power transmission chain of the present invention is formed of two parallel chains that are phased or offset by approximately one-half pitch. The chains are connected by struts that extend across the entire width of both chains. The power transmission chain belt of this invention provides for a restricting device in the interchain gap of the load block. Offset occurring during the speed change of a continuously variable transmission can be absorbed by the above mentioned gap. In one embodiment, the restricting device is in the form of a stop ring provided near the middle of the gap between the two side-by-side chains.
摘要翻译：本发明的动力传递链由两个平行的链构成，这些平行链被相位或偏移大约一半的间距。这些链通过跨越两条链的整个宽度的支柱连接。本发明的传动链带提供了负载块的链间间隙中的限制装置。在无级变速器的变速期间发生的偏移可以被上述间隙吸收。在一个实施例中，限制装置是设置在两个并排链之间的间隙中间附近的止动环的形式。

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