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1. 发明授权

US08536017B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08536017B2
公开(公告)日：2013-09-17
申请号：US13363312
申请日：2012-01-31
申请人： Masaru Kadoshima , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Masaru Kadoshima , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
摘要翻译：在半导体衬底的主表面上形成聚硅氮烷膜，使得埋在宽度为0.2μm或更小的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平，埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

2. 发明申请

US20120208346A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120208346A1
公开(公告)日：2012-08-16
申请号：US13363312
申请日：2012-01-31
申请人： Masaru KADOSHIMA , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Masaru KADOSHIMA , Hiroshi Umeda , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 μm or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 μm or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.
摘要翻译：在半导体衬底的主表面上形成聚硅氮烷膜，使得掩埋在宽度为0.2μm以下的沟槽中的聚硅氮烷膜的上表面水平高于衬垫绝缘膜的上表面水平，埋入宽度为1.0μm以上的沟槽中的聚硅氮烷膜的水平比焊垫绝缘膜低。然后，在300℃以上进行热处理，将聚硅氮烷膜转换为由氧化硅（SiO 2）构成的第一掩埋膜，并且在较窄的沟槽的上部除去空隙。

3. 发明申请

US20100283108A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100283108A1
公开(公告)日：2010-11-11
申请号：US12765571
申请日：2010-04-22
申请人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L27/088 , H01L29/06 , H01L21/762
CPC分类号： H01L29/0653 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02337 , H01L21/3105 , H01L21/76205 , H01L21/76229 , H01L27/088
摘要： To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
摘要翻译：提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

4. 发明授权

US08384187B2 Semiconductor device with shallow trench isolation 有权
标题翻译：具有浅沟槽隔离的半导体器件
公开(公告)号：US08384187B2
公开(公告)日：2013-02-26
申请号：US12765571
申请日：2010-04-22
申请人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
发明人： Mahito Sawada , Tatsunori Kaneoka , Katsuyuki Horita
IPC分类号： H01L21/762
CPC分类号： H01L29/0653 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02337 , H01L21/3105 , H01L21/76205 , H01L21/76229 , H01L27/088
摘要： To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
摘要翻译：提供一种具有能够阻碍对半导体元件的电特性的不利影响的元件隔离结构的半导体器件及其制造方法。留在具有相对窄的宽度的浅沟槽隔离中的第一氧化硅膜的厚度比留在具有较宽宽度的浅沟槽隔离中的第一氧化硅膜薄。通过HDP-CVD法具有相对高的压缩应力的第二氧化硅膜（上层）通过第一氧化硅膜的厚度较薄地层叠在下层的第一氧化硅膜上。最终形成在具有相对窄的宽度的浅沟槽隔离中的元件隔离氧化膜的压缩应力被更强化。

5. 发明申请

US20050269602A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050269602A1
公开(公告)日：2005-12-08
申请号：US11144816
申请日：2005-06-06
申请人： Yoshiki Maruyama , Tatsunori Kaneoka , Toshiya Uenishi
发明人： Yoshiki Maruyama , Tatsunori Kaneoka , Toshiya Uenishi
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8239 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/76224 , H01L27/1052 , H01L29/78
摘要： The inner wall of a trench formed in an element isolation region on a silicon substrate is oxidized to form an inner wall oxide film. The inner wall oxide film is subjected to two nitridation steps including thermal nitridation and radical nitridation. A first nitride layer is formed by the thermal nitridation near the interface between the inner wall oxide film and the silicon substrate. A second nitride layer is formed on a surface of the inner wall oxide film by the radical nitridation. In the thermal nitridation, the amount of nitrogen to be introduced is limited such that a semiconductor element to be formed in an active region is not degraded in reliability.
摘要翻译：形成在硅衬底上的元件隔离区域中的沟槽的内壁被氧化以形成内壁氧化物膜。对内壁氧化膜进行包括热氮化和自由基氮化的两个氮化步骤。通过在内壁氧化膜和硅衬底之间的界面附近的热氮化形成第一氮化物层。通过自由基氮化在内壁氧化膜的表面上形成第二氮化物层。在热氮化中，要引入的氮的量受到限制，使得在有源区中形成的半导体元件的可靠性不会降低。

6. 发明授权

US5902702A Phase shift mask, blank for phase shift mask, and method of manufacturing phase shift mask 失效
标题翻译：相移掩模，相移掩模的空白和相移掩模的制造方法
公开(公告)号：US5902702A
公开(公告)日：1999-05-11
申请号：US745556
申请日：1996-11-12
申请人： Shuji Nakao , Kouichirou Tsujita , Tatsunori Kaneoka
发明人： Shuji Nakao , Kouichirou Tsujita , Tatsunori Kaneoka
IPC分类号： G03F1/00 , G03F1/30 , G03F1/68 , G03F1/80 , H01L21/027 , G03F9/00 , B32B9/00
CPC分类号： G03F1/72 , G03F1/30
摘要： A silicon nitride film and a silicon oxide film are deposited on a transparent substrate 1 to cover a first light transmitting region and to expose a second light transmitting region. A light blocking film is formed in a light blocking region sandwiched between the first and the second light transmitting regions Ta and Tn to cover the transparent substrate 1. A phase shift mask, a blank for a phase shift mask, and a method of manufacturing a phase shift mask are accordingly obtained in which the phase difference of the light transmitted through the light transmitting regions adjacent to each other with the light blocking film interposed is substantially 180.degree. and the intensity of each transmitting light is identical.
摘要翻译：在透明基板1上沉积氮化硅膜和氧化硅膜以覆盖第一透光区域并露出第二透光区域。在夹在第一和第二透光区域Ta和Tn之间的遮光区域中形成遮光膜以覆盖透明基板1.相移掩模，用于相移掩模的坯料，以及制造方法因此得到相位移掩模，其中通过夹持有遮光膜的彼此相邻的透光区域的光的相位差基本上为180°，每个透射光的强度相同。

7. 发明申请

US20060166440A1 Semiconductor nonvolatile memory device, and manufacturing method thereof 审中-公开
标题翻译：半导体非易失性存储器件及其制造方法
公开(公告)号：US20060166440A1
公开(公告)日：2006-07-27
申请号：US11335504
申请日：2006-01-20
申请人： Tatsunori Kaneoka , Yoshiki Maruyama , Satoshi Yamamoto , Toshiya Uenishi
发明人： Tatsunori Kaneoka , Yoshiki Maruyama , Satoshi Yamamoto , Toshiya Uenishi
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L21/0214 , H01L21/02312 , H01L21/02332 , H01L21/28202 , H01L21/3144 , H01L27/115 , H01L27/11521 , H01L29/513 , H01L29/518
摘要： The present invention realizes a semiconductor nonvolatile memory device where a leak current does not easily flow through a tunnel insulating film, and a manufacturing method thereof A silicon nitride oxide film constituting a tunnel insulating film is formed by radically nitriding a surface of a silicon oxide film. The film formed by a radical nitriding process makes it difficult for defects to occur in the film, in comparison with a nitride film formed by a CVD method. In addition, the radical nitriding process causes less plasma damage, in comparison with a conventional simple plasma nitriding process. It is therefore possible to obtain a semiconductor nonvolatile memory device where a leak current does not easily flow through a tunnel insulating film.
摘要翻译：本发明实现了漏电流不容易流过隧道绝缘膜的半导体非易失性存储装置及其制造方法。构成隧道绝缘膜的氮氧化硅膜通过对氧化硅膜的表面进行氮化而形成。与通过CVD法形成的氮化物膜相比，通过自由基氮化处理形成的膜使得难以在膜中发生缺陷。此外，与常规的简单等离子体氮化处理相比，自由基渗氮工艺引起较少的等离子体损伤。因此，可以获得泄漏电流不容易流过隧道绝缘膜的半导体非易失性存储器件。

8. 发明授权

US06448189B1 Method of manufacturing a semiconductor memory device having a capacitor with improved dielectric layer 有权
公开(公告)号：US06448189B1
公开(公告)日：2002-09-10
申请号：US10059122
申请日：2002-01-31
申请人： Tatsunori Kaneoka
发明人： Tatsunori Kaneoka
IPC分类号： H01L21336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531 , H01L28/40
摘要： In the manufacture of a semiconductor memory device having a capacitor formed by arranging a dielectric film including two layers of a silicon oxide film and a silicon nitride film between two electrode films, a thin dielectric film is formed by forming the silicon nitride film on a silicon conductive film by thermally nitriding said silicon conductive film using NO gas, then laminating a silicon oxide film on said silicon nitride film by a CVD method. The erasing/writing speed of semiconductor memory devices, in particular of flash memories or the like, is improved.

9. 发明授权

US08288232B2 Manufacturing method of semiconductor device and semiconductor device 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08288232B2
公开(公告)日：2012-10-16
申请号：US12687110
申请日：2010-01-13
申请人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
发明人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823418 , H01L21/823456 , H01L21/823481 , H01L29/0653 , H01L29/42364
摘要： An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor.
摘要翻译：提供一种半导体器件的制造成品率的提高，该半导体器件包括其中栅绝缘膜具有不同厚度的晶体管。在硅衬底上形成高耐压绝缘膜之后，高耐压绝缘膜的表面被磨损以减小其厚度，使得中间击穿电压绝缘膜形成为邻近高耐压绝缘膜。高耐压绝缘膜通过热氧化法形成，以从硅衬底的主表面的内部延伸到其外部。中间击穿电压绝缘膜形成为比高击穿电压绝缘膜薄。高击穿电压绝缘膜形成为高击穿电压MIS晶体管的栅极绝缘膜，而中间击穿电压绝缘膜形成为中间击穿电压MIS晶体管的栅极绝缘膜。

10. 发明授权

US08372718B2 Manufacturing method of semiconductor device and semiconductor device 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08372718B2
公开(公告)日：2013-02-12
申请号：US13607804
申请日：2012-09-10
申请人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
发明人： Yasuhiro Fujii , Kazumasa Yonekura , Tatsunori Kaneoka
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , H01L21/823418 , H01L21/823456 , H01L21/823481 , H01L29/0653 , H01L29/42364
摘要： An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor.
摘要翻译：提供一种半导体器件的制造成品率的提高，该半导体器件包括其中栅绝缘膜具有不同厚度的晶体管。在硅衬底上形成高耐压绝缘膜之后，高耐压绝缘膜的表面被磨损以减小其厚度，使得中间击穿电压绝缘膜形成为邻近高耐压绝缘膜。高耐压绝缘膜通过热氧化法形成，以从硅衬底的主表面的内部延伸到其外部。中间击穿电压绝缘膜形成为比高击穿电压绝缘膜薄。高击穿电压绝缘膜形成为高击穿电压MIS晶体管的栅极绝缘膜，而中间击穿电压绝缘膜形成为中间击穿电压MIS晶体管的栅极绝缘膜。

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