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1. 发明申请

US20060027883A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060027883A1
公开(公告)日：2006-02-09
申请号：US11241921
申请日：2005-10-04
申请人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
发明人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
IPC分类号： H01L29/94
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method. An MOSFET has a trench-type element isolation structure (2) formed in the main surface of a semiconductor substrate (1), a pair of extensions (3) and source/drain regions (4) selectively formed in the main surface of the semiconductor substrate (1) to face each other through a channel region (50), a silicon oxide film (5) formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) formed on sides of the silicon oxide film (5), a gate insulating film (7) formed on the main surface of the semiconductor substrate (1) in the part in which the channel region (50) is formed, and a gate electrode (8) formed to fill a recessed portion in an inversely tapered form formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译：本发明的目的是获得其中通道长度减小而不增加栅极电阻以实现更高的操作速度的半导体器件及其制造方法。 MOSFET具有形成在半导体衬底（1）的主表面中的沟槽型元件隔离结构（2），在半导体的主表面中选择性地形成的一对延伸部（3）和源极/漏极区域（4）衬底（1）通过沟道区域（50）彼此面对，通过硅氧化膜形成在沟槽型元件隔离结构（2）上和源极/漏极区域（4）上的氧化硅膜（5）（12），形成在氧化硅膜（5）的侧面上的侧壁（6），形成在半导体衬底（1）的主表面上的沟道区域（50）的部分中的栅极绝缘膜（7）以及形成为以由侧壁（6）的侧面和栅极绝缘膜（7）的上表面形成的倒锥形状填充凹部的栅电极（8）。

2. 发明授权

US06661066B2 Semiconductor device including inversely tapered gate electrode and manufacturing method thereof 失效
标题翻译：包括反锥形栅电极的半导体器件及其制造方法
公开(公告)号：US06661066B2
公开(公告)日：2003-12-09
申请号：US09401849
申请日：1999-09-22
申请人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
发明人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
IPC分类号： H01L31119
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译：一种半导体器件和制造方法，包括形成在半导体衬底（1）的主表面上的沟槽型元件隔离结构（2）的MOSFET。在主表面中选择性地形成一对延伸部（3）和源极/漏极区域（4），以便通过沟道区域（50）彼此面对，在沟槽型（5）上形成氧化硅膜元件隔离结构（2），并且通过氧化硅膜（12）在源极/漏极区域（4）上，在氧化硅膜（5）的侧面上形成侧壁（6），栅极绝缘膜（7）为形成在形成有沟道区域（50）的部分的主表面上，并且形成栅电极（8）以填充由侧壁（6）的侧面和上表面形成的倒锥形状的凹部的栅极绝缘膜（7）。

3. 发明授权

US06548871B1 Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer 失效
标题翻译：半导体器件通过在相同的线层中形成第一层布线和栅极上电极来实现缩短的布线长度并减少布线延迟
公开(公告)号：US06548871B1
公开(公告)日：2003-04-15
申请号：US09543349
申请日：2000-04-05
申请人： Katsuyuki Horita , Takashi Kuroi , Yasuyoshi Itoh , Katsuomi Shiozawa
发明人： Katsuyuki Horita , Takashi Kuroi , Yasuyoshi Itoh , Katsuomi Shiozawa
IPC分类号： H01L2976
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/823475 , H01L23/522 , H01L23/535 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.
摘要翻译：属于彼此相邻的分离元件的两个源极/漏极区域（20）通过与形成栅电极的一部分的金属层（10）的高度相同的高度的金属层（14）连接。在制造过程中，绝缘层（8）由除两个绝缘层（7）和（16）之外的其它材料制成。两个绝缘层（7）和（16）作为用于将金属层（10），（14）和（15）埋入其中并由相同材料制成的模具。因此，金属层（14）可以形成在与金属层（10）的高度相同的高度。因此，通过布置在较短距离处的布线而连接的部分被连接，同时降低布线能力。

4. 发明授权

US06383884B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06383884B1
公开(公告)日：2002-05-07
申请号：US09496057
申请日：2000-02-02
申请人： Katsuomi Shiozawa , Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita
发明人： Katsuomi Shiozawa , Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28247 , H01L29/66537
摘要： A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5). A method of manufacturing the semiconductor device is provided which attains reduction in gate length without the decrease in driving capability to accomplish the increase in operating speed.
摘要翻译：半导体器件包括硅衬底（1），一对隔离绝缘膜（9），沟道区（2），一对源/漏区（3），一对氧化硅膜（4），形成在硅衬底（1）的上表面覆盖在源极/漏极区（3）上，并且栅极结构（8）形成在由硅衬底（1）的上表面限定的第一凹部中，沟道区域（2）和一对氧化硅膜（4）的侧表面。栅极结构（8）包括形成在硅衬底（1）的上表面上的栅氧化膜（5），一对氧化硅膜（6），形成在该一对氧化硅的侧表面的下部以及填充由氧化硅膜（4）的侧面的上部，氧化硅膜（6）和栅极氧化膜（5）所包围的第二凹部的金属膜（7）。提供了一种制造半导体器件的方法，其在不降低驱动能力的情况下实现栅极长度的减小以实现操作速度的提高。

5. 发明授权

US06737315B2 Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate 失效
标题翻译：制造半导体器件的方法包括在衬底上形成绝缘膜和外延半导体的步骤
公开(公告)号：US06737315B2
公开(公告)日：2004-05-18
申请号：US10212249
申请日：2002-08-06
申请人： Takashi Kuroi , Katsuyuki Horita , Katsuomi Shiozawa
发明人： Takashi Kuroi , Katsuyuki Horita , Katsuomi Shiozawa
IPC分类号： H01L218242
CPC分类号： H01L21/762 , H01L21/823481 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.
摘要翻译：将基板表面（10S）热氧化以形成氧化膜。图案化氧化膜，使得有源区域中的衬底表面（10S）暴露。由此提供氧化膜（20）。暴露的衬底表面（10S）被热氧化，以形成热氧化膜。此后，至少在元件形成区域中除去该热氧化膜。在暴露的基板表面（10S）上外延生长硅膜（41）。此后，通过CMP对硅膜（41）进行抛光，使抛光后的硅膜的上表面的高度不超过氧化膜（20）的上表面。接着，将硅膜的表面热氧化，形成热氧化膜。在各种类型的离子注入之后，去除该热氧化膜。

6. 发明授权

US06707099B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06707099B2
公开(公告)日：2004-03-16
申请号：US10218444
申请日：2002-08-15
申请人： Katsuomi Shiozawa , Takashi Kuroi , Katsuyuki Horita
发明人： Katsuomi Shiozawa , Takashi Kuroi , Katsuyuki Horita
IPC分类号： H01L29792
CPC分类号： H01L29/66651 , H01L21/28123 , H01L29/1033
摘要： A semiconductor device less susceptible to inverse narrow channel effect and its manufacturing method are provided. A silicon nitride film (13) is adopted as element isolation regions; the silicon nitride film (13) has a smaller etch rate than a sacrificial silicon oxide film (7) which serves as a sacrificial layer during ion implantation (8). This prevents formation of recesses in the silicon nitride film (13) during the removal of the sacrificial silicon oxide film (7), which weakens the strength of the electric fields at the gate edges. Weakening the strength of the electric fields at the gate edges suppresses the inverse narrow channel effect, so that the MOS transistor offers a characteristic closer to a characteristic in which the threshold voltage keeps a constant value independently of the channel width. Thus an MOS transistor having a good characteristic can be manufactured.
摘要翻译：提供了一种不易反向窄通道效应的半导体器件及其制造方法。采用氮化硅膜（13）作为元件隔离区域; 氮化硅膜（13）具有比在离子注入期间用作牺牲层的牺牲氧化硅膜（7）更小的蚀刻速率（8）。这样可以防止在去除牺牲氧化硅膜（7）期间在氮化硅膜（13）中形成凹陷，这削弱了栅极边缘处的电场强度。削弱栅极边缘处的电场强度抑制了反向窄通道效应，使得MOS晶体管具有更接近阈值电压独立于沟道宽度保持恒定值的特性。因此，可以制造具有良好特性的MOS晶体管。

7. 发明授权

US06890837B2 Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate 失效
标题翻译：制造半导体器件的方法包括在衬底上形成绝缘膜和外延半导体的步骤
公开(公告)号：US06890837B2
公开(公告)日：2005-05-10
申请号：US10683359
申请日：2003-10-14
申请人： Takashi Kuroi , Katsuyuki Horita , Katsuomi Shiozawa
发明人： Takashi Kuroi , Katsuyuki Horita , Katsuomi Shiozawa
IPC分类号： H01L21/28 , H01L21/20 , H01L21/76 , H01L21/762 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L23/544 , H01L27/04 , H01L27/08 , H01L27/092 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78 , H01L21/46
CPC分类号： H01L21/762 , H01L21/823481 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.
摘要翻译：衬底表面（10S）被热氧化以形成氧化物膜。图案化氧化膜，使得有源区域中的衬底表面（10S）暴露。由此提供氧化膜（20）。暴露的衬底表面（10S）被热氧化，以形成热氧化膜。此后，至少在元件形成区域中除去该热氧化膜。在暴露的基板表面（10S）上外延生长硅膜（41）。此后，通过CMP对硅膜（41）进行抛光，使抛光后的硅膜的上表面的高度不超过氧化膜（20）的上表面。接着，将硅膜的表面热氧化，形成热氧化膜。在各种类型的离子注入之后，去除该热氧化膜。

8. 发明授权

US06482718B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06482718B2
公开(公告)日：2002-11-19
申请号：US09963432
申请日：2001-09-27
申请人： Katsuomi Shiozawa , Takashi Kuroi , Katsuyuki Horita
发明人： Katsuomi Shiozawa , Takashi Kuroi , Katsuyuki Horita
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76235
摘要： A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).
摘要翻译：提供一种制造半导体器件的方法，即使器件尺寸减小，也可以防止沟槽隔离结构中的元件隔离区彼此隔离的半导体元件的工作特性的劣化。通过氮化硅膜（2）将离子（15）从上方注入到多晶硅层（3）中产生离子注入的多晶硅层（16）。由于离子（15）是用于增强氧化的元素的离子种类，离子（15）的注入将多晶硅层（3）改变为具有较高氧化速率的离子注入的多晶硅层（16）。在随后在沟槽（5）的内壁上形成热氧化膜（21）时，离子注入的多晶硅层（16）的暴露部分也被氧化，形成相当宽的多晶硅氧化物区域（21a）。

9. 发明授权

US06387743B1 Semiconductor device manufacturing method and semiconductor device 失效
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US06387743B1
公开(公告)日：2002-05-14
申请号：US09978540
申请日：2001-10-18
申请人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
发明人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
IPC分类号： H01L218238
CPC分类号： H01L21/82385 , H01L21/823842 , H01L21/823864
摘要： A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.
摘要翻译：一种能够在绝缘栅晶体管中形成浅扩展区的半导体器件和制造方法。含有约1〜20％磷的侧壁材料（如PSG）沉积在开口的两侧至几十纳米至约100nm的膜厚度并被回蚀以形成分别毗邻的含磷侧壁含硼侧壁。然后在氮化硅膜上形成氮化硅等的层间绝缘膜。在形成层间绝缘膜期间进行的热处理通过扩散形成NMOS区域中的N型延伸区域，其中含磷侧壁中的磷用作扩散源，PMOS区域中的P型延伸区域通过包含在含硼侧壁中的硼用作扩散源的扩散。

10. 发明授权

US06333540B1 Semiconductor device manufacturing method and semiconductor device 失效
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US06333540B1
公开(公告)日：2001-12-25
申请号：US09668472
申请日：2000-09-25
申请人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
发明人： Katsuomi Shiozawa , Syuichi Ueno , Yasuyoshi Itoh
IPC分类号： H01L2701
CPC分类号： H01L21/82385 , H01L21/823842 , H01L21/823864
摘要： A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.
摘要翻译：一种能够在绝缘栅晶体管中形成浅扩展区的半导体器件和制造方法。含有约1〜20％磷的侧壁材料（如PSG）沉积在开口的两侧至几十纳米至约100nm的膜厚度并被回蚀以形成分别毗邻的含磷侧壁含硼侧壁。然后在氮化硅膜上形成氮化硅等的层间绝缘膜。在形成层间绝缘膜期间进行的热处理通过扩散形成NMOS区域中的N型延伸区域，其中含磷侧壁中的磷用作扩散源，PMOS区域中的P型延伸区域通过包含在含硼侧壁中的硼用作扩散源的扩散。

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