专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08390062B2 Vertical channel transistor array and manufacturing method thereof 有权
标题翻译：垂直沟道晶体管阵列及其制造方法
公开(公告)号：US08390062B2
公开(公告)日：2013-03-05
申请号：US12839412
申请日：2010-07-20
申请人： Heiji Kobayashi , Yukihiro Nagai
发明人： Heiji Kobayashi , Yukihiro Nagai
IPC分类号： H01L29/66
CPC分类号： H01L21/762 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10894
摘要： A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
摘要翻译：垂直沟道晶体管阵列具有由多个半导体柱形成的有源区。多个嵌入式位线平行布置在半导体衬底中并沿列方向延伸。多个位线触点分别设置在一个嵌入位线的一侧。多个嵌入字线平行地布置在嵌入式位线上方并沿行方向延伸。此外，嵌入字线将同一行中的半导体柱与夹在嵌入字线和半导体柱之间的栅介质层连接。电流泄漏隔离结构设置在嵌入式位线的端子处，以防止相邻位线触点之间的电流泄漏。

2. 发明授权

US07691713B2 Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film 失效
标题翻译：制造半导体器件的方法，该半导体器件能够抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低
公开(公告)号：US07691713B2
公开(公告)日：2010-04-06
申请号：US11767734
申请日：2007-06-25
申请人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
发明人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
摘要翻译：提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。在形成氧化硅膜（20）和氮化硅膜（21）的情况下，沿着Y方向从对角线上方注入p型杂质离子（23,23,2）。至于植入角度。采用满足关系tan-1（W2 / T）<α＆nlE; tan-1（W1 / T）的植入角度，其中W1是第一部分（211）和第四部分（214）和第三部分（213）和第六部分（216）之间的间隔; W2是第二部分（212）和第五部分（215）之间的间隔; T是氧化硅膜（20）和氮化硅膜（21）的总膜厚。当将注入角度α控制在该范围内时，杂质离子（231,231）通过氧化硅膜（13）注入第二侧面（10A2）和第五侧面（10A5）。

3. 发明申请

US20070243687A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULTING FILM 失效
标题翻译：制造半导体器件的方法，其能够抑制由形成绝缘膜形成的掺杂通道区域中的浓度浓度降低
公开(公告)号：US20070243687A1
公开(公告)日：2007-10-18
申请号：US11767734
申请日：2007-06-25
申请人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
发明人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (23.sub.1, 23.sub.2) are implanted in a Y direction from diagonally above. As for an implant angle .alpha. of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
摘要翻译：提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。在形成有氧化硅膜（20）和氮化硅膜（21）的情况下，将p型杂质离子（23,2,2,3 ...）从对角线方向注入Y方向。至于植入角度。的离子注入，采用满足tan <-1≤（W 2 / T）<α<= TAN-1（W 1 / T）的关系的注入角度，其中W 1是第一部分（21 <1> 1）和第四部分（21 <4>）之间的间隔，以及第三部分（21,33）之间的间隔）和第六部分（21×6）; W 2是第二部分（21 ... 2）与第五部分（21 ... 5）之间的间隔; T是氧化硅膜（20）和氮化硅膜（21）的总膜厚。当将注入角度α控制在该范围内时，杂质离子（23×1，23×1）被注入到第二侧表面（10A / SUB>）和通过氧化硅膜（13）的第五侧表面（10 A 5 S）。

4. 发明授权

US06229172B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06229172B1
公开(公告)日：2001-05-08
申请号：US09192461
申请日：1998-11-16
申请人： Heiji Kobayashi
发明人： Heiji Kobayashi
IPC分类号： H01L2972
CPC分类号： H01L27/10894 , H01L27/10852
摘要： A semiconductor device having a gentle step between a memory cell array region and a peripheral region is provided, in which the resist at this portion can be prevented from being reduced in thickness. The semiconductor device includes a memory cell block having a plurality of capacitors and formed on the main surface of a silicon substrate. An outer surface of the end portion of the capacitor in the memory cell block has an upper surface extending at a first height above the main surface of the silicon substrate, and contiguous with the upper surface, a bottom surface extending at a second height lower than the first height above the main surface of the silicon substrate.
摘要翻译：提供了一种在存储单元阵列区域和周边区域之间具有缓和台阶的半导体器件，其中可以防止该部分处的抗蚀剂的厚度减小。半导体器件包括具有多个电容器并形成在硅衬底的主表面上的存储单元块。存储单元块中的电容器的端部的外表面具有在硅衬底的主表面上方的第一高度处延伸的上表面，并且与上表面邻接，底表面在低于硅衬底主表面上方的第一高度。

5. 发明授权

US06215187B1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06215187B1
公开(公告)日：2001-04-10
申请号：US09400857
申请日：1999-09-21
申请人： Kenichi Ooto , Heiji Kobayashi , Shouitirou Nakazawa
发明人： Kenichi Ooto , Heiji Kobayashi , Shouitirou Nakazawa
IPC分类号： H01L2348
CPC分类号： H01L28/91 , H01L21/31111 , H01L21/76804 , H01L27/10814 , H01L27/10852 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and manufacturing method thereof attaining higher capacitor capacitance and lower power consumption are provided. On an interlayer oxide film which is a BPTEOS film containing an impurity, an interlayer oxide film which is a TEOS film not containing any impurity is formed. Openings of approximately inverted frusto-conical shape of approximately the same size are formed in interlayer oxide films, respectively, providing a contact hole of such a shape that includes two inverted frusto-cones continued in the vertical direction as a whole is provided. Along the inner wall surface of the contact hole, a storage electrode, a dielectric film and a cell plate electrode constituting a capacitor are formed successively.
摘要翻译：提供一种半导体器件及其获得更高电容器电容和降低功耗的制造方法。在作为含有杂质的BPTEOS膜的层间氧化膜上形成不含有杂质的TEOS膜的层间氧化膜。大致相同大小的倒立的截头圆锥形的开口分别形成在层间氧化膜中，从而提供了包括沿垂直方向连续连续的两个反向截头圆锥体的这种形状的接触孔。沿着接触孔的内壁面，依次形成存储电极，电介质膜和构成电容器的电池板电极。

6. 外观设计

USD278892S Snowmobile 失效
公开(公告)号：USD278892S
公开(公告)日：1985-05-21
申请号：US451793
申请日：1982-12-21
申请人： Heiji Kobayashi
设计人： Heiji Kobayashi

7. 发明申请

US20100190306A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING IMPURITY CONCENTRATION REDUCTION IN DOPED CHANNEL REGION ARISING FROM FORMATION OF GATE INSULATING FILM 审中-公开
标题翻译：制造半导体器件的方法，其能够抑制由形成绝缘膜形成的掺杂通道区域中的浓度浓度降低
公开(公告)号：US20100190306A1
公开(公告)日：2010-07-29
申请号：US12754097
申请日：2010-04-05
申请人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
发明人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
IPC分类号： H01L21/336 , H01L21/02
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1 (W2/T)
摘要翻译：提供一种制造半导体器件的方法，其可以抑制由栅极绝缘膜形成引起的掺杂沟道区域中的杂质浓度降低。在形成氧化硅膜和氮化硅膜的情况下，在对角上方沿Y方向注入p型杂质离子。对于离子注入的注入角度α，采用满足关系tan-1（W2 / T）<α＆nlE; tan-1（W1 / T）的植入角度，其中W1是第一部分和第四部分和第三部分和第六部分之间的间隔; W2是第二部分和第五部分之间的间隔; T是氧化硅膜和氮化硅膜的总膜厚。当将注入角度α控制在该范围内时，杂质离子通过氧化硅膜注入第二侧表面和第五侧表面。

8. 发明授权

US06998319B2 Method of manufacturing semiconductor device capable of suppressing impurity concentration reduction in doped channel region arising from formation of gate insulating film 失效
公开(公告)号：US06998319B2
公开(公告)日：2006-02-14
申请号：US10730099
申请日：2003-12-09
申请人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
发明人： Yoshinori Tanaka , Katsuyuki Horita , Heiji Kobayashi
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/26586 , H01L27/10817 , H01L27/10894 , H01L27/10897 , H01L29/78
摘要： A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film (20) and a silicon nitride film (21) being formed, p-type impurity ions (231, 232) are implanted in a Y direction from diagonally above. As for an implant angle α of the ion implantation, an implant angle is adopted that satisfies the relationship tan−1(W2/T)

9. 发明授权

US06815265B2 Method of fabricating a semiconductor device with a passivation film 失效
标题翻译：制造具有钝化膜的半导体器件的方法
公开(公告)号：US06815265B2
公开(公告)日：2004-11-09
申请号：US10202042
申请日：2002-07-25
申请人： Shinya Nakatani , Heiji Kobayashi
发明人： Shinya Nakatani , Heiji Kobayashi
IPC分类号： H01L2182
CPC分类号： H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An uppermost interlayer isolation film is provided on a semiconductor substrate. An uppermost wire is provided on the uppermost interlayer isolation film. A silicon oxide film is provided to cover the upper surface and the side wall of the uppermost wire. A nitride film is provided on the uppermost interlayer isolation film to cover the uppermost wire through the silicon oxide film. A polyimide film is provided on the nitride film. A portion of the uppermost interlayer isolation film other than a portion located under the uppermost wire is downwardly scooped. The nitride film covers the scooped portion of the uppermost interlayer isolation film. According to the present invention, a semiconductor device improved to be capable of improving coverage of a silicon nitride passivation film is obtained.
摘要翻译：在半导体衬底上设置最上层的隔离膜。最上层的金属丝设置在最上层的层间隔离膜上。提供氧化硅膜以覆盖最上面的电线的上表面和侧壁。在最上层的层间绝缘膜上设置氮化膜，以覆盖通过氧化硅膜的最上面的导线。在氮化膜上设置聚酰亚胺膜。最上面的层间绝缘膜除了位于最上面的线之下的部分之外，部分被向下舀取。氮化物膜覆盖最上层间隔离膜的舀取部分。根据本发明，可以获得改善为能够提高氮化硅钝化膜的覆盖率的半导体器件。

10. 发明授权

US5478759A Method of manufacturing semiconductor device with retrograde wells 失效
标题翻译：制造具有逆行井的半导体器件的方法
公开(公告)号：US5478759A
公开(公告)日：1995-12-26
申请号：US156748
申请日：1993-11-24
申请人： Tomoharu Mametani , Masahiro Shimizu , Katsuhiro Tsukamoto , Hajime Arai , Heiji Kobayashi
发明人： Tomoharu Mametani , Masahiro Shimizu , Katsuhiro Tsukamoto , Hajime Arai , Heiji Kobayashi
IPC分类号： H01L21/761 , H01L21/265 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L21/266
CPC分类号： H01L21/823878 , H01L21/76218 , H01L27/0921 , H01L27/1052
摘要： A thick isolation oxide film is selectively formed on a surface of a silicon substrate so as to isolate an element formation region. Ions are implanted into a region in silicon substrate through the thick isolation oxide film. Thus, retrograde wells, having impurity concentration peak positions are formed in the region of silicon substrate positioned under the isolation oxide film. Then, an upper part of the isolation oxide film is removed away to form an isolation oxide film with a reduced thickness. Isolation oxide film has a reduced isolation length L. Thus, a semiconductor device is provided, which permits restriction of the narrow channel effect and the substrate biasing effect when the size of elements is reduced.
摘要翻译：在硅衬底的表面上选择性地形成厚的隔离氧化膜，以隔离元件形成区域。离子通过厚的隔离氧化膜植入到硅衬底的区域中。因此，在位于隔离氧化膜下方的硅衬底的区域中形成具有杂质浓度峰值位置的逆行阱。然后，去除隔离氧化膜的上部，形成厚度减小的隔离氧化膜。隔离氧化膜具有减小的隔离长度L.因此，提供了一种半导体器件，当元件的尺寸减小时，允许限制窄沟道效应和衬底偏置效应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式